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author | jhb <jhb@FreeBSD.org> | 2014-02-12 04:30:37 +0000 |
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committer | jhb <jhb@FreeBSD.org> | 2014-02-12 04:30:37 +0000 |
commit | 6e6e271c34f0bc0881fd2171f9d0709306b2eb8c (patch) | |
tree | 4ed418e09d2abca6c5033a32710e2f5170bc5bb4 /sys/sparc64/pci | |
parent | b3e5336bce93d0b0b1c4b9735fe419d1585ae53e (diff) | |
download | FreeBSD-src-6e6e271c34f0bc0881fd2171f9d0709306b2eb8c.zip FreeBSD-src-6e6e271c34f0bc0881fd2171f9d0709306b2eb8c.tar.gz |
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge
I/O windows, the default is to preserve the firmware-assigned resources.
PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture
defines a PCI_RES_BUS resource type.
- Add a helper API to create top-level PCI bus resource managers for each
PCI domain/segment. Host-PCI bridge drivers use this API to allocate
bus numbers from their associated domain.
- Change the PCI bus and CardBus drivers to allocate a bus resource for
their bus number from the parent PCI bridge device.
- Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the
full range of bus numbers from secbus to subbus from their parent bridge.
The drivers also always program their primary bus register. The bridge
drivers also support growing their bus range by extending the bus resource
and updating subbus to match the larger range.
- Add support for managing PCI bus resources to the Host-PCI bridge drivers
used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib).
- Define a PCI_RES_BUS resource type for amd64 and i386.
Reviewed by: imp
MFC after: 1 month
Diffstat (limited to 'sys/sparc64/pci')
-rw-r--r-- | sys/sparc64/pci/apb.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/sys/sparc64/pci/apb.c b/sys/sparc64/pci/apb.c index a6854e9..9b3fa44 100644 --- a/sys/sparc64/pci/apb.c +++ b/sys/sparc64/pci/apb.c @@ -177,9 +177,9 @@ apb_attach(device_t dev) pci_read_config(dev, PCIR_COMMAND, 2); sc->sc_bsc.ops_pcib_sc.pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1); - sc->sc_bsc.ops_pcib_sc.secbus = + sc->sc_bsc.ops_pcib_sc.bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1); - sc->sc_bsc.ops_pcib_sc.subbus = + sc->sc_bsc.ops_pcib_sc.bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); sc->sc_bsc.ops_pcib_sc.bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); @@ -200,10 +200,10 @@ apb_attach(device_t dev) CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.pribus, 0, "Primary bus number"); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", - CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.secbus, 0, + CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.bus.sec, 0, "Secondary bus number"); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", - CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.subbus, 0, + CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.bus.sub, 0, "Subordinate bus number"); ofw_pcib_gen_setup(dev); @@ -212,9 +212,9 @@ apb_attach(device_t dev) device_printf(dev, " domain %d\n", sc->sc_bsc.ops_pcib_sc.domain); device_printf(dev, " secondary bus %d\n", - sc->sc_bsc.ops_pcib_sc.secbus); + sc->sc_bsc.ops_pcib_sc.bus.sec); device_printf(dev, " subordinate bus %d\n", - sc->sc_bsc.ops_pcib_sc.subbus); + sc->sc_bsc.ops_pcib_sc.bus.sub); device_printf(dev, " I/O decode "); apb_map_print(sc->sc_iomap, APB_IO_SCALE); printf("\n"); |