Add a driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo'

JBus to PCI 2.2 bridges. In theory, this driver should also handle
`XMITS' Fireplane/Safari to PCI-X bridges but due to lack of access
to such hardware, support for these hasn't be fleshed out, yet.

3 files changed, 1649 insertions, 0 deletions

diff --git a/sys/sparc64/pci/schizo.c b/sys/sparc64/pci/schizo.c
new file mode 100644
index 0000000..214fb92
--- /dev/null
+++ b/sys/sparc64/pci/schizo.c
@@ -0,0 +1,1266 @@
+/*-
+ * Copyright (c) 1999, 2000 Matthew R. Green
+ * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
+ * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
+ *	from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to
+ * PCI 2.2 bridges
+ */
+
+#include "opt_ofw_pci.h"
+#include "opt_schizo.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/pcpu.h>
+#include <sys/rman.h>
+#include <sys/timetc.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_pci.h>
+#include <dev/ofw/openfirm.h>
+
+#include <machine/bus.h>
+#include <machine/bus_common.h>
+#include <machine/bus_private.h>
+#include <machine/fsr.h>
+#include <machine/iommureg.h>
+#include <machine/iommuvar.h>
+#include <machine/ofw_bus.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <sparc64/pci/ofw_pci.h>
+#include <sparc64/pci/schizoreg.h>
+#include <sparc64/pci/schizovar.h>
+
+#include "pcib_if.h"
+
+static const struct schizo_desc *schizo_get_desc(device_t);
+static void schizo_set_intr(struct schizo_softc *, u_int, u_int,
+    driver_filter_t);
+static driver_filter_t schizo_dmasync;
+static void schizo_intr_enable(void *);
+static void schizo_intr_disable(void *);
+static void schizo_intr_assign(void *);
+static void schizo_intr_clear(void *);
+static int schizo_get_intrmap(struct schizo_softc *, u_int,
+    bus_addr_t *, bus_addr_t *);
+static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int);
+static timecounter_get_t schizo_get_timecount;
+
+/* Interrupt handlers */
+static driver_filter_t schizo_pci_bus;
+static driver_filter_t schizo_ue;
+static driver_filter_t schizo_ce;
+static driver_filter_t schizo_host_bus;
+
+/* IOMMU support */
+static void schizo_iommu_init(struct schizo_softc *, int, uint32_t);
+
+/*
+ * Methods
+ */
+static device_probe_t schizo_probe;
+static device_attach_t schizo_attach;
+static bus_read_ivar_t schizo_read_ivar;
+static bus_setup_intr_t schizo_setup_intr;
+static bus_teardown_intr_t schizo_teardown_intr;
+static bus_alloc_resource_t schizo_alloc_resource;
+static bus_activate_resource_t schizo_activate_resource;
+static bus_deactivate_resource_t schizo_deactivate_resource;
+static bus_release_resource_t schizo_release_resource;
+static bus_get_dma_tag_t schizo_get_dma_tag;
+static pcib_maxslots_t schizo_maxslots;
+static pcib_read_config_t schizo_read_config;
+static pcib_write_config_t schizo_write_config;
+static pcib_route_interrupt_t schizo_route_interrupt;
+static ofw_bus_get_node_t schizo_get_node;
+
+static device_method_t schizo_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		schizo_probe),
+	DEVMETHOD(device_attach,	schizo_attach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	DEVMETHOD(device_suspend,	bus_generic_suspend),
+	DEVMETHOD(device_resume,	bus_generic_resume),
+
+	/* Bus interface */
+	DEVMETHOD(bus_print_child,	bus_generic_print_child),
+	DEVMETHOD(bus_read_ivar,	schizo_read_ivar),
+	DEVMETHOD(bus_setup_intr,	schizo_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	schizo_teardown_intr),
+	DEVMETHOD(bus_alloc_resource,	schizo_alloc_resource),
+	DEVMETHOD(bus_activate_resource,	schizo_activate_resource),
+	DEVMETHOD(bus_deactivate_resource,	schizo_deactivate_resource),
+	DEVMETHOD(bus_release_resource,	schizo_release_resource),
+	DEVMETHOD(bus_get_dma_tag,	schizo_get_dma_tag),
+
+	/* pcib interface */
+	DEVMETHOD(pcib_maxslots,	schizo_maxslots),
+	DEVMETHOD(pcib_read_config,	schizo_read_config),
+	DEVMETHOD(pcib_write_config,	schizo_write_config),
+	DEVMETHOD(pcib_route_interrupt,	schizo_route_interrupt),
+
+	/* ofw_bus interface */
+	DEVMETHOD(ofw_bus_get_node,	schizo_get_node),
+
+	{ 0, 0 }
+};
+
+static devclass_t schizo_devclass;
+
+DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods,
+    sizeof(struct schizo_softc));
+DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0);
+
+static SLIST_HEAD(, schizo_softc) schizo_softcs =
+    SLIST_HEAD_INITIALIZER(schizo_softcs);
+
+static const struct intr_controller schizo_ic = {
+	schizo_intr_enable,
+	schizo_intr_disable,
+	schizo_intr_assign,
+	schizo_intr_clear
+};
+
+struct schizo_icarg {
+	struct schizo_softc	*sica_sc;
+	bus_addr_t		sica_map;
+	bus_addr_t		sica_clr;
+};
+
+struct schizo_dmasync {
+	struct schizo_softc	*sds_sc;
+	driver_filter_t		*sds_handler;
+	void			*sds_arg;
+	void			*sds_cookie;
+	bus_size_t		sds_syncreg;
+	uint64_t		sds_syncval;
+	u_int			sds_bswar;
+};
+
+#define	SCHIZO_PERF_CNT_QLTY	100
+
+#define	SCHIZO_SPC_READ_8(spc, sc, offs) \
+	bus_read_8((sc)->sc_mem_res[(spc)], (offs))
+#define	SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \
+	bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v))
+
+#define	SCHIZO_PCI_READ_8(sc, offs) \
+	SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs))
+#define	SCHIZO_PCI_WRITE_8(sc, offs, v) \
+	SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v))
+#define	SCHIZO_CTRL_READ_8(sc, offs) \
+	SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs))
+#define	SCHIZO_CTRL_WRITE_8(sc, offs, v) \
+	SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v))
+#define	SCHIZO_PCICFG_READ_8(sc, offs) \
+	SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs))
+#define	SCHIZO_PCICFG_WRITE_8(sc, offs, v) \
+	SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v))
+#define	SCHIZO_ICON_READ_8(sc, offs) \
+	SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs))
+#define	SCHIZO_ICON_WRITE_8(sc, offs, v) \
+	SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v))
+
+#define	OFW_PCI_TYPE		"pci"
+
+struct schizo_desc {
+	const char	*sd_string;
+	int		sd_mode;
+	const char	*sd_name;
+};
+
+static const struct schizo_desc schizo_compats[] = {
+	{ "pci108e,8001",	SCHIZO_MODE_SCZ,	"Schizo" },
+	{ "pci108e,a801",	SCHIZO_MODE_TOM,	"Tomatillo" },
+	{ NULL,			0,			NULL }
+};
+
+static const struct schizo_desc *
+schizo_get_desc(device_t dev)
+{
+	const struct schizo_desc *desc;
+	const char *compat;
+
+	compat = ofw_bus_get_compat(dev);
+	if (compat == NULL)
+		return (NULL);
+	for (desc = schizo_compats; desc->sd_string != NULL; desc++)
+		if (strcmp(desc->sd_string, compat) == 0)
+			return (desc);
+	return (NULL);
+}
+
+static int
+schizo_probe(device_t dev)
+{
+	const char *dtype;
+
+	dtype = ofw_bus_get_type(dev);
+	if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 &&
+	    schizo_get_desc(dev) != NULL) {
+		device_set_desc(dev, "Sun Host-PCI bridge");
+		return (0);
+	}
+	return (ENXIO);
+}
+
+static int
+schizo_attach(device_t dev)
+{
+	struct ofw_pci_ranges *range;
+	const struct schizo_desc *desc;
+	struct schizo_icarg *sica;
+	struct schizo_softc *asc, *sc, *osc;
+	struct timecounter *tc;
+	bus_addr_t intrclr, intrmap;
+	uint64_t ino_bitmap, reg;
+	phandle_t node;
+	uint32_t prop, prop_array[2];
+	int i, mode, n, nrange, rid, tsbsize;
+
+	sc = device_get_softc(dev);
+	node = ofw_bus_get_node(dev);
+	desc = schizo_get_desc(dev);
+	mode = desc->sd_mode;
+
+	sc->sc_dev = dev;
+	sc->sc_node = node;
+	sc->sc_mode = mode;
+
+	/*
+	 * The Schizo has three register banks:
+	 * (0) per-PBM PCI configuration and status registers, but for bus B
+	 *     shared with the UPA64s interrupt mapping register banks
+	 * (1) shared Schizo controller configuration and status registers
+	 * (2) per-PBM PCI configuration space
+	 *
+	 * The Tomatillo has four register banks:
+	 * (0) per-PBM PCI configuration and status registers
+	 * (1) per-PBM Tomatillo controller configuration registers, but on
+	 *     machines having the `jbusppm' device shared with its Estar
+	 *     register bank for bus A
+	 * (2) per-PBM PCI configuration space
+	 * (3) per-PBM interrupt concentrator registers
+	 */
+	sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >>
+	    20) & 1;
+	for (n = 0; n < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG);
+	    n++) {
+		rid = n;
+		sc->sc_mem_res[n] = bus_alloc_resource_any(dev,
+		    SYS_RES_MEMORY, &rid,
+		    (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 &&
+		    n == STX_PCI) || n == STX_CTRL)) ||
+		    (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 &&
+		    n == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE);
+		if (sc->sc_mem_res[n] == NULL)
+			panic("%s: could not allocate register bank %d",
+			    __func__, n);
+	}
+
+	/*
+	 * Match other Schizos that are already configured against
+	 * the controller base physical address.  This will be the
+	 * same for a pair of devices that share register space.
+	 */
+	osc = NULL;
+	SLIST_FOREACH(asc, &schizo_softcs, sc_link) {
+		if (rman_get_start(asc->sc_mem_res[STX_CTRL]) ==
+		    rman_get_start(sc->sc_mem_res[STX_CTRL])) {
+			/* Found partner. */
+			osc = asc;
+			break;
+		}
+	}
+	if (osc == NULL) {
+		sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
+		    M_NOWAIT | M_ZERO);
+		if (sc->sc_mtx == NULL)
+			panic("%s: could not malloc mutex", __func__);
+		mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
+	} else {
+		if (mtx_initialized(osc->sc_mtx) == 0)
+			panic("%s: mutex not initialized", __func__);
+		sc->sc_mtx = osc->sc_mtx;
+	}
+
+	if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1)
+		panic("%s: could not determine IGN", __func__);
+	if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == -1)
+		panic("%s: could not determine version", __func__);
+	if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
+		prop = 33000000;
+
+	device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n",
+	    desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half,
+	    prop / 1000 / 1000);
+
+	/* Set up the PCI interrupt retry timer. */
+#ifdef SCHIZO_DEBUG
+	device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long)
+	    SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM));
+#endif
+	SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5);
+
+	/* Set up the PCI control register. */
+	reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
+	reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN |
+	    STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK;
+	reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK);
+	if (OF_getproplen(node, "no-bus-parking") < 0)
+		reg |= STX_PCI_CTRL_ARB_PARK;
+	if (mode == SCHIZO_MODE_TOM) {
+		reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL;
+		if (sc->sc_ver <= 1)	/* revision <= 2.0 */
+			reg |= TOM_PCI_CTRL_DTO_IEN;
+		else
+			reg |= STX_PCI_CTRL_PTO;
+	}
+#ifdef SCHIZO_DEBUG
+	device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
+	    (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL),
+	    (unsigned long long)reg);
+#endif
+	SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg);
+
+	/* Set up the PCI diagnostic register. */
+	reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG);
+	reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS |
+	    STX_PCI_DIAG_INTRSYNC_DIS);
+#ifdef SCHIZO_DEBUG
+	device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
+	    (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG),
+	    (unsigned long long)reg);
+#endif
+	SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg);
+
+	/*
+	 * On Tomatillo clear the I/O prefetch lengths (workaround for a
+	 * Jalapeno bug).
+	 */
+	if (mode == SCHIZO_MODE_TOM)
+		SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW |
+		    (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM |
+		    TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL);
+
+	/*
+	 * Hunt through all the interrupt mapping regs and register
+	 * the interrupt controller for our interrupt vectors.  This
+	 * is complicated by the fact that a pair of Schizo PBMs
+	 * share one IGN.
+	 */
+	n = OF_getprop(node, "ino-bitmap", (void *)prop_array,
+	    sizeof(prop_array));
+	if (n == -1)
+		panic("%s: could not get ino-bitmap", __func__);
+	ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0];
+	for (n = 0; n <= STX_MAX_INO; n++) {
+		if ((ino_bitmap & (1ULL << n)) == 0)
+			continue;
+		if (n == STX_FB0_INO || n == STX_FB1_INO)
+			/* Leave for upa(4). */
+			continue;
+		if (schizo_get_intrmap(sc, n, &intrmap, &intrclr) == 0)
+			continue;
+		sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT);
+		if (sica == NULL)
+			panic("%s: could not allocate interrupt controller "
+			    "argument", __func__);
+		sica->sica_sc = sc;
+		sica->sica_map = intrmap;
+		sica->sica_clr = intrclr;
+#ifdef SCHIZO_DEBUG
+		device_printf(dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n",
+		    n, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap),
+		    (u_long)intrclr);
+#endif
+		if (intr_controller_register(INTMAP_VEC(sc->sc_ign, n),
+		    &schizo_ic, sica) != 0)
+			panic("%s: could not register interrupt controller "
+			    "for INO %d", __func__, n);
+	}
+
+	/*
+	 * Setup Safari/JBus performance counter 0 in bus cycle counting
+	 * mode as timecounter.  Unfortunately, this is broken with at
+	 * least the version 4 Tomatillos found in Fire V120 and Blade
+	 * 1500, which apparently actually count some different event at
+	 * ~0.5 and 3MHz respectively instead (also when running in full
+	 * power mode).  Besides, one counter seems to be shared by a
+	 * "pair" of Tomatillos, too.
+	 */
+	if (sc->sc_half == 0) {
+		SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF,
+		    (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) |
+		    (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT));
+		tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO);
+		if (tc == NULL)
+			panic("%s: could not malloc timecounter", __func__);
+		tc->tc_get_timecount = schizo_get_timecount;
+		tc->tc_poll_pps = NULL;
+		tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK;
+		if (OF_getprop(OF_peer(0), "clock-frequency", &prop,
+		    sizeof(prop)) == -1)
+			panic("%s: could not determine clock frequency",
+			    __func__);
+		tc->tc_frequency = prop;
+		tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF);
+		if (mode == SCHIZO_MODE_SCZ)
+			tc->tc_quality = SCHIZO_PERF_CNT_QLTY;
+		else
+			tc->tc_quality = -SCHIZO_PERF_CNT_QLTY;
+		tc->tc_priv = sc;
+		tc_init(tc);
+	}
+
+	/* Set up the IOMMU.  Both Schizo and Tomatillo have one per PBM. */
+	sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS);
+	sc->sc_is.is_sb[0] = 0;
+	sc->sc_is.is_sb[1] = 0;
+	if (OF_getproplen(node, "no-streaming-cache") < 0)
+		sc->sc_is.is_sb[0] = STX_PCI_STRBUF;
+
+#define	TSBCASE(x)							\
+	case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT):	\
+		tsbsize = (x);						\
+		break;							\
+
+	n = OF_getprop(node, "virtual-dma", (void *)prop_array,
+	    sizeof(prop_array));
+	if (n == -1 || n != sizeof(prop_array))
+		schizo_iommu_init(sc, 7, -1);
+	else {
+		switch (prop_array[1]) {
+		TSBCASE(1);
+		TSBCASE(2);
+		TSBCASE(3);
+		TSBCASE(4);
+		TSBCASE(5);
+		TSBCASE(6);
+		TSBCASE(7);
+		TSBCASE(8);
+		default:
+			panic("%s: unsupported DVMA size 0x%x",
+			    __func__, prop_array[1]);
+			/* NOTREACHED */
+		}
+		schizo_iommu_init(sc, tsbsize, prop_array[0]);
+	}
+#undef TSBCASE
+
+	/* Initialize memory and I/O rmans. */
+	sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
+	sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports";
+	if (rman_init(&sc->sc_pci_io_rman) != 0 ||
+	    rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0)
+		panic("%s: failed to set up I/O rman", __func__);
+	sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
+	sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory";
+	if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
+	    rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0)
+		panic("%s: failed to set up memory rman", __func__);
+
+	nrange = OF_getprop_alloc(node, "ranges", sizeof(*range),
+	    (void **)&range);
+	/*
+	 * Make sure that the expected ranges are present.  The
+	 * OFW_PCI_CS_MEM64 one is not currently used though.
+	 */
+	if (nrange != STX_NRANGE)
+		panic("%s: unsupported number of ranges", __func__);
+	/*
+	 * Find the addresses of the various bus spaces.
+	 * There should not be multiple ones of one kind.
+	 * The physical start addresses of the ranges are the configuration,
+	 * memory and I/O handles.
+	 */
+	for (n = 0; n < STX_NRANGE; n++) {
+		i = OFW_PCI_RANGE_CS(&range[n]);
+		if (sc->sc_pci_bh[i] != 0)
+			panic("%s: duplicate range for space %d", __func__, i);
+		sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]);
+	}
+	free(range, M_OFWPROP);
+
+	/* Register the softc, this is needed for paired Schizos. */
+	SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link);
+
+	/* Allocate our tags. */
+	sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
+	sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
+	sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE);
+	if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
+	    sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr,
+	    0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
+		panic("%s: bus_dma_tag_create failed", __func__);
+	/* Customize the tag. */
+	sc->sc_pci_dmat->dt_cookie = &sc->sc_is;
+	sc->sc_pci_dmat->dt_mt = &iommu_dma_methods;
+
+	/*
+	 * Get the bus range from the firmware.
+	 * NB: Tomatillos don't support PCI bus reenumeration.
+	 */
+	n = OF_getprop(node, "bus-range", (void *)prop_array,
+	    sizeof(prop_array));
+	if (n == -1)
+		panic("%s: could not get bus-range", __func__);
+	if (n != sizeof(prop_array))
+		panic("%s: broken bus-range (%d)", __func__, n);
+	if (bootverbose)
+		device_printf(dev, "bus range %u to %u; PCI bus %d\n",
+		    prop_array[0], prop_array[1], prop_array[0]);
+	sc->sc_pci_secbus = prop_array[0];
+
+	/* Clear any pending PCI error bits. */
+	PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
+	    PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
+	    STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2);
+	SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL,
+	    SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL));
+	SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR,
+	    SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR));
+
+	/*
+	 * Establish handlers for interesting interrupts...
+	 * Someone at Sun clearly was smoking crack; with Schizos PCI
+	 * bus error interrupts for one PBM can be routed to the other
+	 * PBM though we obviously need to use the softc of the former
+	 * as the argument for the interrupt handler and the softc of
+	 * the latter as the argument for the interrupt controller.
+	 */
+	if (sc->sc_half == 0) {
+		if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 ||
+		    (osc != NULL && ((struct schizo_icarg *)intr_vectors[
+		    INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)->
+		    sica_sc == osc))
+			/*
+			 * We are the driver for PBM A and either also
+			 * registered the interrupt controller for us or
+			 * the driver for PBM B has probed first and
+			 * registered it for us.
+			 */
+			schizo_set_intr(sc, 0, STX_PCIERR_A_INO,
+			    schizo_pci_bus);
+		if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 &&
+		    osc != NULL)
+			/*
+			 * We are the driver for PBM A but registered
+			 * the interrupt controller for PBM B, i.e. the
+			 * driver for PBM B attached first but couldn't
+			 * set up a handler for PBM B.
+			 */
+			schizo_set_intr(osc, 0, STX_PCIERR_B_INO,
+			    schizo_pci_bus);
+	} else {
+		if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 ||
+		    (osc != NULL && ((struct schizo_icarg *)intr_vectors[
+		    INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)->
+		    sica_sc == osc))
+			/*
+			 * We are the driver for PBM B and either also
+			 * registered the interrupt controller for us or
+			 * the driver for PBM A has probed first and
+			 * registered it for us.
+			 */
+			schizo_set_intr(sc, 0, STX_PCIERR_B_INO,
+			    schizo_pci_bus);
+		if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 &&
+		    osc != NULL)
+			/*
+			 * We are the driver for PBM B but registered
+			 * the interrupt controller for PBM A, i.e. the
+			 * driver for PBM A attached first but couldn't
+			 * set up a handler for PBM A.
+			 */
+			schizo_set_intr(osc, 0, STX_PCIERR_A_INO,
+			    schizo_pci_bus);
+	}
+	if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0)
+		schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue);
+	if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0)
+		schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce);
+	if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0)
+		schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus);
+
+	/*
+	 * Set the latency timer register as this isn't always done by the
+	 * firmware.
+	 */
+	PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
+	    PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
+
+	ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
+
+	device_add_child(dev, "pci", -1);
+	return (bus_generic_attach(dev));
+}
+
+static void
+schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino,
+    driver_filter_t handler)
+{
+	u_long vec;
+	int rid;
+
+	rid = index;
+	sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ,
+	    &rid, RF_ACTIVE);
+	if (sc->sc_irq_res[index] == NULL ||
+	    INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign ||
+	    INTINO(vec) != ino ||
+	    intr_vectors[vec].iv_ic != &schizo_ic ||
+	    bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], INTR_TYPE_MISC,
+	    handler, NULL, sc, &sc->sc_ihand[index]) != 0)
+		panic("%s: failed to set up interrupt %d", __func__, index);
+}
+
+static int
+schizo_get_intrmap(struct schizo_softc *sc, u_int ino, bus_addr_t *intrmapptr,
+    bus_addr_t *intrclrptr)
+{
+	bus_addr_t intrclr, intrmap;
+	uint64_t mr;
+
+	/*
+	 * XXX we only look for INOs rather than INRs since the firmware
+	 * may not provide the IGN and the IGN is constant for all devices
+	 * on that PCI controller.
+	 */
+
+	if (ino > STX_MAX_INO) {
+		device_printf(sc->sc_dev, "out of range INO %d requested\n",
+		    ino);
+		return (0);
+	}
+
+	intrmap = STX_PCI_IMAP_BASE + (ino << 3);
+	intrclr = STX_PCI_ICLR_BASE + (ino << 3);
+	mr = SCHIZO_PCI_READ_8(sc, intrmap);
+	if (INTINO(mr) != ino) {
+		device_printf(sc->sc_dev,
+		    "interrupt map entry does not match INO (%d != %d)\n",
+		    (int)INTINO(mr), ino);
+		return (0);
+	}
+
+	if (intrmapptr != NULL)
+		*intrmapptr = intrmap;
+	if (intrclrptr != NULL)
+		*intrclrptr = intrclr;
+	return (1);
+}
+
+/*
+ * Interrupt handlers
+ */
+static int
+schizo_pci_bus(void *arg)
+{
+	struct schizo_softc *sc = arg;
+	uint64_t afar, afsr, csr, iommu;
+	uint32_t status;
+
+	afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR);
+	afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR);
+	csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
+	iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU);
+	status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus,
+	    STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
+	if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) {
+		if ((iommu & TOM_PCI_IOMMU_ERR) == 0)
+			goto clear_error;
+
+		/* These are non-fatal if target abort was signaled. */
+		if ((status & PCIM_STATUS_STABORT) != 0 &&
+		    ((iommu & TOM_PCI_IOMMU_ERRMASK) ==
+		    TOM_PCI_IOMMU_INVALID_ERR ||
+		    (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 ||
+		    (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) {
+			SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu);
+			goto clear_error;
+		}
+	}
+
+	panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx "
+	    "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev),
+	    'A' + sc->sc_half, (unsigned long long)afar,
+	    (unsigned long long)afsr, (unsigned long long)csr,
+	    (unsigned long long)iommu, (unsigned long long)status);
+
+ clear_error:
+	if (bootverbose)
+		device_printf(sc->sc_dev,
+		    "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx "
+		    "STATUS %#llx", 'A' + sc->sc_half,
+		    (unsigned long long)afar, (unsigned long long)afsr,
+		    (unsigned long long)csr, (unsigned long long)status);
+	/* Clear the error bits that we caught. */
+	PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE,
+	    STX_CS_FUNC, PCIR_STATUS, status, 2);
+	SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
+	SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
+	return (FILTER_HANDLED);
+}
+
+static int
+schizo_ue(void *arg)
+{
+	struct schizo_softc *sc = arg;
+	uint64_t afar, afsr;
+	int i;
+
+	mtx_lock_spin(sc->sc_mtx);
+	afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR);
+	for (i = 0; i < 1000; i++)
+		if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
+		    STX_CTRL_CE_AFSR_ERRPNDG) == 0)
+			break;
+	mtx_unlock_spin(sc->sc_mtx);
+	panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx",
+	    device_get_name(sc->sc_dev), (unsigned long long)afar,
+	    (unsigned long long)afsr);
+	return (FILTER_HANDLED);
+}
+
+static int
+schizo_ce(void *arg)
+{
+	struct schizo_softc *sc = arg;
+	uint64_t afar, afsr;
+	int i;
+
+	mtx_lock_spin(sc->sc_mtx);
+	afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR);
+	for (i = 0; i < 1000; i++)
+		if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
+		    STX_CTRL_CE_AFSR_ERRPNDG) == 0)
+			break;
+	device_printf(sc->sc_dev,
+	    "correctable DMA error AFAR %#llx AFSR %#llx\n",
+	    (unsigned long long)afar, (unsigned long long)afsr);
+	/* Clear the error bits that we caught. */
+	SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr);
+	mtx_unlock_spin(sc->sc_mtx);
+	return (FILTER_HANDLED);
+}
+
+static int
+schizo_host_bus(void *arg)
+{
+	struct schizo_softc *sc = arg;
+	uint64_t errlog;
+
+	errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG);
+	panic("%s: %s error %#llx", device_get_name(sc->sc_dev),
+	    sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari",
+	    (unsigned long long)errlog);
+	return (FILTER_HANDLED);
+}
+
+static void
+schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase)
+{
+
+	/* Punch in our copies. */
+	sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
+	sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]);
+	sc->sc_is.is_iommu = STX_PCI_IOMMU;
+	sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG;
+	sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG;
+	sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG;
+	sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG;
+	sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG;
+
+	iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize,
+	    dvmabase, 0);
+}
+
+static int
+schizo_maxslots(device_t dev)
+{
+	struct schizo_softc *sc;
+
+	sc = device_get_softc(dev);
+	if (sc->sc_mode == SCHIZO_MODE_SCZ)
+		return (sc->sc_half == 0 ? 4 : 6);
+
+	/* XXX: is this correct? */
+	return (PCI_SLOTMAX);
+}
+
+static uint32_t
+schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
+    int width)
+{
+	struct schizo_softc *sc;
+	bus_space_handle_t bh;
+	u_long offset = 0;
+	uint32_t r, wrd;
+	int i;
+	uint16_t shrt;
+	uint8_t byte;
+
+	sc = device_get_softc(dev);
+
+	/*
+	 * The Schizo bridges contain a dupe of their header at 0x80.
+	 */
+	if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus &&
+	    slot == STX_CS_DEVICE && func == STX_CS_FUNC &&
+	    reg + width > 0x80)
+		return (0);
+
+	offset = STX_CONF_OFF(bus, slot, func, reg);
+	bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
+	switch (width) {
+	case 1:
+		i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
+		r = byte;
+		break;
+	case 2:
+		i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
+		r = shrt;
+		break;
+	case 4:
+		i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
+		r = wrd;
+		break;
+	default:
+		panic("%s: bad width", __func__);
+		/* NOTREACHED */
+	}
+
+	if (i) {
+#ifdef SCHIZO_DEBUG
+		printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
+		    __func__, bus, slot, func, reg);
+#endif
+		r = -1;
+	}
+	return (r);
+}
+
+static void
+schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
+    uint32_t val, int width)
+{
+	struct schizo_softc *sc;
+	bus_space_handle_t bh;
+	u_long offset = 0;
+
+	sc = device_get_softc(dev);
+	offset = STX_CONF_OFF(bus, slot, func, reg);
+	bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
+	switch (width) {
+	case 1:
+		bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
+		break;
+	case 2:
+		bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
+		break;
+	case 4:
+		bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
+		break;
+	default:
+		panic("%s: bad width", __func__);
+		/* NOTREACHED */
+	}
+}
+
+static int
+schizo_route_interrupt(device_t bridge, device_t dev, int pin)
+{
+	struct schizo_softc *sc;
+	struct ofw_pci_register reg;
+	ofw_pci_intr_t pintr, mintr;
+	uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
+
+	sc = device_get_softc(bridge);
+	pintr = pin;
+	if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, &reg,
+	    sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf))
+		return (mintr);
+
+	device_printf(bridge, "could not route pin %d for device %d.%d\n",
+	    pin, pci_get_slot(dev), pci_get_function(dev));
+	return (PCI_INVALID_IRQ);
+}
+
+static int
+schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+	struct schizo_softc *sc;
+
+	sc = device_get_softc(dev);
+	switch (which) {
+	case PCIB_IVAR_DOMAIN:
+		*result = device_get_unit(dev);
+		return (0);
+	case PCIB_IVAR_BUS:
+		*result = sc->sc_pci_secbus;
+		return (0);
+	}
+	return (ENOENT);
+}
+
+#define	VIS_BLOCKSIZE	64
+
+static int
+schizo_dmasync(void *arg)
+{
+	static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE);
+	struct schizo_dmasync *sds = arg;
+	struct schizo_softc *sc = sds->sds_sc;
+	uint64_t reg;
+	int timeout;
+
+	SCHIZO_PCI_WRITE_8(sc, sds->sds_syncreg, sds->sds_syncval);
+	timeout = 1000000;
+	for (; (SCHIZO_PCI_READ_8(sc, sds->sds_syncreg) &
+	    sds->sds_syncval) != 0;)
+		if (--timeout < 0)
+			panic("%s: DMA does not sync", __func__);
+
+	if (sds->sds_bswar != 0) {
+		critical_enter();
+		reg = rd(fprs);
+		wr(fprs, reg | FPRS_FEF, 0);
+		__asm__ __volatile__("stda %%f0, [%0] %1"
+		    : : "r" (buf), "n" (ASI_BLK_COMMIT_S));
+		wr(fprs, reg, 0);
+		membar(Sync);
+		critical_exit();
+	}
+	return (sds->sds_handler(sds->sds_arg));
+}
+
+static void
+schizo_intr_enable(void *arg)
+{
+	struct intr_vector *iv = arg;
+	struct schizo_icarg *sica = iv->iv_icarg;
+
+	SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map,
+	    INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
+}
+
+static void
+schizo_intr_disable(void *arg)
+{
+	struct intr_vector *iv = arg;
+	struct schizo_icarg *sica = iv->iv_icarg;
+
+	SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec);
+}
+
+static void
+schizo_intr_assign(void *arg)
+{
+	struct intr_vector *iv = arg;
+	struct schizo_icarg *sica = iv->iv_icarg;
+
+	SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID(
+	    SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid));
+}
+
+static void
+schizo_intr_clear(void *arg)
+{
+	struct intr_vector *iv = arg;
+	struct schizo_icarg *sica = iv->iv_icarg;
+
+	SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0);
+}
+
+static int
+schizo_setup_intr(device_t dev, device_t child, struct resource *ires,
+    int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
+    void **cookiep)
+{
+	struct schizo_dmasync *sds;
+	struct schizo_softc *sc;
+	u_long vec;
+	int error;
+
+	sc = device_get_softc(dev);
+	/*
+	 * Make sure the vector is fully specified and we registered
+	 * our interrupt controller for it.
+	 */
+	vec = rman_get_start(ires);
+	if (INTIGN(vec) != sc->sc_ign ||
+	    intr_vectors[vec].iv_ic != &schizo_ic) {
+		device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
+		return (EINVAL);
+	}
+
+	/*
+	 * Schizo revision >= 2.3 (i.e. version >= 5) and Tomatillo bridges
+	 * need to be manually told to sync DMA writes.
+	 * Tomatillo revision <= 2.3 (i.e. version <= 4) bridges additionally
+	 * need a block store as a workaround for a hardware bug.
+	 * XXX setup of the wrapper and the contents of schizo_dmasync()
+	 * should be moved to schizo(4)-specific bus_dma_tag_create() and
+	 * bus_dmamap_sync() methods, respectively, once DMA tag creation
+	 * is newbus'ified, so the wrapper isn't only applied for interrupt
+	 * handlers but also for polling(4) callbacks.
+	 */
+	if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) ||
+	    sc->sc_mode == SCHIZO_MODE_TOM) {
+		sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO);
+		if (sds == NULL)
+			return (ENOMEM);
+		sds->sds_sc = sc;
+		sds->sds_arg = arg;
+		sds->sds_syncreg = sc->sc_mode == SCHIZO_MODE_SCZ ?
+		    SCZ_PCI_DMA_SYNC : TOMXMS_PCI_DMA_SYNC_PEND;
+		sds->sds_syncval = 1ULL << INTINO(vec);
+		if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4)
+			sds->sds_bswar = 1;
+		if (intr == NULL) {
+			sds->sds_handler = filt;
+			error = bus_generic_setup_intr(dev, child, ires,
+			    flags, schizo_dmasync, intr, sds, cookiep);
+		} else {
+			sds->sds_handler = (driver_filter_t *)intr;
+			error = bus_generic_setup_intr(dev, child, ires,
+			    flags, filt, (driver_intr_t *)schizo_dmasync,
+			    sds, cookiep);
+		}
+		if (error != 0) {
+			free(sds, M_DEVBUF);
+			return (error);
+		}
+		sds->sds_cookie = *cookiep;
+		*cookiep = sds;
+		return (error);
+	}
+	return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
+	    arg, cookiep));
+}
+
+static int
+schizo_teardown_intr(device_t dev, device_t child, struct resource *vec,
+    void *cookie)
+{
+	struct schizo_dmasync *sds;
+	struct schizo_softc *sc;
+	int error;
+
+	sc = device_get_softc(dev);
+	if (sc->sc_mode == SCHIZO_MODE_TOM) {
+		sds = cookie;
+		error = bus_generic_teardown_intr(dev, child, vec,
+		    sds->sds_cookie);
+		if (error == 0)
+			free(sds, M_DEVBUF);
+		return (error);
+	}
+	return (bus_generic_teardown_intr(dev, child, vec, cookie));
+}
+
+static struct resource *
+schizo_alloc_resource(device_t bus, device_t child, int type, int *rid,
+    u_long start, u_long end, u_long count, u_int flags)
+{
+	struct schizo_softc *sc;
+	struct resource *rv;
+	struct rman *rm;
+	bus_space_tag_t bt;
+	bus_space_handle_t bh;
+	int needactivate = flags & RF_ACTIVE;
+
+	flags &= ~RF_ACTIVE;
+
+	sc = device_get_softc(bus);
+	if (type == SYS_RES_IRQ) {
+		/*
+		 * XXX: Don't accept blank ranges for now, only single
+		 * interrupts.  The other case should not happen with
+		 * the MI PCI code...
+		 * XXX: This may return a resource that is out of the
+		 * range that was specified.  Is this correct...?
+		 */
+		if (start != end)
+			panic("%s: XXX: interrupt range", __func__);
+		start = end = INTMAP_VEC(sc->sc_ign, end);
+		return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
+		    rid, start, end, count, flags));
+	}
+	switch (type) {
+	case SYS_RES_MEMORY:
+		rm = &sc->sc_pci_mem_rman;
+		bt = sc->sc_pci_memt;
+		bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32];
+		break;
+	case SYS_RES_IOPORT:
+		rm = &sc->sc_pci_io_rman;
+		bt = sc->sc_pci_iot;
+		bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
+		break;
+	default:
+		return (NULL);
+		/* NOTREACHED */
+	}
+
+	rv = rman_reserve_resource(rm, start, end, count, flags, child);
+	if (rv == NULL)
+		return (NULL);
+	rman_set_rid(rv, *rid);
+	bh += rman_get_start(rv);
+	rman_set_bustag(rv, bt);
+	rman_set_bushandle(rv, bh);
+
+	if (needactivate) {
+		if (bus_activate_resource(child, type, *rid, rv)) {
+			rman_release_resource(rv);
+			return (NULL);
+		}
+	}
+	return (rv);
+}
+
+static int
+schizo_activate_resource(device_t bus, device_t child, int type, int rid,
+    struct resource *r)
+{
+	void *p;
+	int error;
+
+	if (type == SYS_RES_IRQ)
+		return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
+		    type, rid, r));
+	if (type == SYS_RES_MEMORY) {
+		/*
+		 * Need to memory-map the device space, as some drivers depend
+		 * on the virtual address being set and useable.
+		 */
+		error = sparc64_bus_mem_map(rman_get_bustag(r),
+		    rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
+		if (error != 0)
+			return (error);
+		rman_set_virtual(r, p);
+	}
+	return (rman_activate_resource(r));
+}
+
+static int
+schizo_deactivate_resource(device_t bus, device_t child, int type, int rid,
+    struct resource *r)
+{
+
+	if (type == SYS_RES_IRQ)
+		return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
+		    type, rid, r));
+	if (type == SYS_RES_MEMORY) {
+		sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
+		rman_set_virtual(r, NULL);
+	}
+	return (rman_deactivate_resource(r));
+}
+
+static int
+schizo_release_resource(device_t bus, device_t child, int type, int rid,
+    struct resource *r)
+{
+	int error;
+
+	if (type == SYS_RES_IRQ)
+		return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
+		    type, rid, r));
+	if (rman_get_flags(r) & RF_ACTIVE) {
+		error = bus_deactivate_resource(child, type, rid, r);
+		if (error)
+			return (error);
+	}
+	return (rman_release_resource(r));
+}
+
+static bus_dma_tag_t
+schizo_get_dma_tag(device_t bus, device_t child)
+{
+	struct schizo_softc *sc;
+
+	sc = device_get_softc(bus);
+	return (sc->sc_pci_dmat);
+}
+
+static phandle_t
+schizo_get_node(device_t bus, device_t dev)
+{
+	struct schizo_softc *sc;
+
+	sc = device_get_softc(bus);
+	/* We only have one child, the PCI bus, which needs our own node. */
+	return (sc->sc_node);
+}
+
+static bus_space_tag_t
+schizo_alloc_bus_tag(struct schizo_softc *sc, int type)
+{
+	bus_space_tag_t bt;
+
+	bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF,
+	    M_NOWAIT | M_ZERO);
+	if (bt == NULL)
+		panic("%s: out of memory", __func__);
+
+	bt->bst_cookie = sc;
+	bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
+	bt->bst_type = type;
+	return (bt);
+}
+
+static u_int
+schizo_get_timecount(struct timecounter *tc)
+{
+	struct schizo_softc *sc;
+
+	sc = tc->tc_priv;
+	return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) &
+	    (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT));
+}
diff --git a/sys/sparc64/pci/schizoreg.h b/sys/sparc64/pci/schizoreg.h
new file mode 100644
index 0000000..f4020ff
--- /dev/null
+++ b/sys/sparc64/pci/schizoreg.h
@@ -0,0 +1,312 @@
+/*-
+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
+ * Copyright (c) 2005 by Marius Strobl <marius@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULLAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *	from: OpenBSD: schizoreg.h,v 1.8 2005/05/19 18:28:59 mickey Exp
+ * $FreeBSD$
+ */
+
+#ifndef _SPARC64_PCI_SCHIZOREG_H_
+#define	_SPARC64_PCI_SCHIZOREG_H_
+
+#define	STX_NINTR			4
+#define	STX_NRANGE			4
+#define	SCZ_NREG			3
+#define	TOM_NREG			4
+
+#define	STX_PCI				0
+#define	STX_CTRL			1
+#define	STX_PCICFG			2
+#define	STX_ICON			3
+
+/* PCI configuration and status registers */
+#define	STX_PCI_IOMMU			0x00200
+#define	STX_PCI_IOMMU_CTXFLUSH		0x00218
+#define	STX_PCI_IMAP_BASE		0x01000
+#define	STX_PCI_ICLR_BASE		0x01400
+#define	STX_PCI_INTR_RETRY_TIM		0x01a00
+#define	SCZ_PCI_DMA_SYNC		0x01a08
+#define	TOM_PCI_DMA_SYNC_COMP		0x01a10
+#define	TOMXMS_PCI_DMA_SYNC_PEND	0x01a18
+#define	STX_PCI_CTRL			0x02000
+#define	STX_PCI_AFSR			0x02010
+#define	STX_PCI_AFAR			0x02018
+#define	STX_PCI_DIAG			0x02020
+#define	TOM_PCI_IOC_CSR			0x02248
+#define	TOM_PCI_IOC_TAG			0x02290
+#define	TOM_PCI_IOC_DATA		0x02290
+#define	STX_PCI_STRBUF			0x02800
+#define	STX_PCI_STRBUF_CTXFLUSH		0x02818
+#define	STX_PCI_IOMMU_SVADIAG		0x0a400
+#define	STX_PCI_IOMMU_TLB_CMP_DIAG	0x0a408
+#define	STX_PCI_IOMMU_QUEUE_DIAG	0x0a500
+#define	STX_PCI_IOMMU_TLB_TAG_DIAG	0x0a580
+#define	STX_PCI_IOMMU_TLB_DATA_DIAG	0x0a600
+#define	STX_PCI_IOBIO_DIAG		0x0a808
+#define	STX_PCI_STRBUF_CTXMATCH		0x10000
+
+/* PCI IOMMU control registers */
+#define	TOM_PCI_IOMMU_ERR_BAD_VA	0x0000000010000000ULL
+#define	TOM_PCI_IOMMU_ERR_ILLTSBTBW	0x0000000008000000ULL
+#define	TOM_PCI_IOMMU_ECC_ERR		0x0000000006000000ULL
+#define	TOM_PCI_IOMMU_TIMEOUT_ERR	0x0000000004000000ULL
+#define	TOM_PCI_IOMMU_INVALID_ERR	0x0000000002000000ULL
+#define	TOM_PCI_IOMMU_PROTECTION_ERR	0x0000000000000000ULL
+#define	TOM_PCI_IOMMU_ERRMASK						\
+	(TOM_PCI_IOMMU_PROTECTION_ERR | TOM_PCI_IOMMU_INVALID_ERR |	\
+	TOM_PCI_IOMMU_TIMEOUT_ERR | TOM_PCI_IOMMU_ECC_ERR)
+#define	TOM_PCI_IOMMU_ERR		0x0000000001000000ULL
+
+/* PCI control/status register */
+#define	SCZ_PCI_CTRL_BUS_UNUS		0x8000000000000000ULL
+#define	TOM_PCI_CTRL_DTO_ERR		0x4000000000000000ULL
+#define	TOM_PCI_CTRL_DTO_IEN		0x2000000000000000ULL
+#define	SCZ_PCI_CTRL_ESLCK		0x0008000000000000ULL
+#define	SCZ_PCI_CTRL_ERRSLOT		0x0007000000000000ULL
+#define	STX_PCI_CTRL_TTO_ERR		0x0000004000000000ULL
+#define	STX_PCI_CTRL_RTRY_ERR		0x0000002000000000ULL
+#define	STX_PCI_CTRL_MMU_ERR		0x0000001000000000ULL
+#define	SCZ_PCI_CTRL_SBH_ERR		0x0000000800000000ULL
+#define	STX_PCI_CTRL_SERR		0x0000000400000000ULL
+#define	SCZ_PCI_CTRL_PCISPD		0x0000000200000000ULL
+#define	TOM_PCI_CTRL_PRM		0x0000000040000000ULL
+#define	TOM_PCI_CTRL_PRO		0x0000000020000000ULL
+#define	TOM_PCI_CTRL_PRL		0x0000000010000000ULL
+#define	STX_PCI_CTRL_PTO		0x0000000003000000ULL
+#define	STX_PCI_CTRL_MMU_IEN		0x0000000000080000ULL
+#define	STX_PCI_CTRL_SBH_IEN		0x0000000000040000ULL
+#define	STX_PCI_CTRL_ERR_IEN		0x0000000000020000ULL
+#define	STX_PCI_CTRL_ARB_PARK		0x0000000000010000ULL
+#define	SCZ_PCI_CTRL_PCIRST		0x0000000000000100ULL
+#define	STX_PCI_CTRL_ARB_MASK		0x00000000000000ffULL
+
+/* PCI asynchronous fault status register */
+#define	STX_PCI_AFSR_P_MA		0x8000000000000000ULL
+#define	STX_PCI_AFSR_P_TA		0x4000000000000000ULL
+#define	STX_PCI_AFSR_P_RTRY		0x2000000000000000ULL
+#define	STX_PCI_AFSR_P_PERR		0x1000000000000000ULL
+#define	STX_PCI_AFSR_P_TTO		0x0800000000000000ULL
+#define	STX_PCI_AFSR_P_UNUS		0x0400000000000000ULL
+#define	STX_PCI_AFSR_S_MA		0x0200000000000000ULL
+#define	STX_PCI_AFSR_S_TA		0x0100000000000000ULL
+#define	STX_PCI_AFSR_S_RTRY		0x0080000000000000ULL
+#define	STX_PCI_AFSR_S_PERR		0x0040000000000000ULL
+#define	STX_PCI_AFSR_S_TTO		0x0020000000000000ULL
+#define	STX_PCI_AFSR_S_UNUS		0x0010000000000000ULL
+#define	STX_PCI_AFSR_DWMASK		0x0000030000000000ULL
+#define	STX_PCI_AFSR_BMASK		0x000000ff00000000ULL
+#define	STX_PCI_AFSR_BLK		0x0000000080000000ULL
+#define	STX_PCI_AFSR_CFG		0x0000000040000000ULL
+#define	STX_PCI_AFSR_MEM		0x0000000020000000ULL
+#define	STX_PCI_AFSR_IO			0x0000000010000000ULL
+
+/* PCI diagnostic register */
+#define	SCZ_PCI_DIAG_BADECC_DIS		0x0000000000000400ULL
+#define	STX_PCI_DIAG_BYPASS_DIS		0x0000000000000200ULL
+#define	STX_PCI_DIAG_TTO_DIS		0x0000000000000100ULL
+#define	SCZ_PCI_DIAG_RTRYARB_DIS	0x0000000000000080ULL
+#define	STX_PCI_DIAG_RETRY_DIS		0x0000000000000040ULL
+#define	STX_PCI_DIAG_INTRSYNC_DIS	0x0000000000000020ULL
+#define	STX_PCI_DIAG_DMAPARITY_INV	0x0000000000000008ULL
+#define	STX_PCI_DIAG_PIODPARITY_INV	0x0000000000000004ULL
+#define	STX_PCI_DIAG_PIOAPARITY_INV	0x0000000000000002ULL
+
+/* Tomatillo I/O cache register */
+#define	TOM_PCI_IOC_PW			0x0000000000080000ULL
+#define	TOM_PCI_IOC_PRM			0x0000000000040000ULL
+#define	TOM_PCI_IOC_PRO			0x0000000000020000ULL
+#define	TOM_PCI_IOC_PRL			0x0000000000010000ULL
+#define	TOM_PCI_IOC_PRM_LEN		0x000000000000c000ULL
+#define	TOM_PCI_IOC_PRM_LEN_SHIFT	14
+#define	TOM_PCI_IOC_PRO_LEN		0x0000000000003000ULL
+#define	TOM_PCI_IOC_PRO_LEN_SHIFT	12
+#define	TOM_PCI_IOC_PRL_LEN		0x0000000000000c00ULL
+#define	TOM_PCI_IOC_PRL_LEN_SHIFT	10
+#define	TOM_PCI_IOC_PREF_OFF		0x0000000000000038ULL
+#define	TOM_PCI_IOC_PREF_OFF_SHIFT	3
+#define	TOM_PCI_IOC_CPRM		0x0000000000000004ULL
+#define	TOM_PCI_IOC_CPRO		0x0000000000000002ULL
+#define	TOM_PCI_IOC_CPRL		0x0000000000000001ULL
+
+/* Controller configuration and status registers */
+/* Note that these are shared on Schizo but per-PBM on Tomatillo. */
+#define	STX_CTRL_BUS_ERRLOG		0x00018
+#define	STX_CTRL_ECCCTRL		0x00020
+#define	STX_CTRL_UE_AFSR		0x00030
+#define	STX_CTRL_UE_AFAR		0x00038
+#define	STX_CTRL_CE_AFSR		0x00040
+#define	STX_CTRL_CE_AFAR		0x00048
+#define	STX_CTRL_PERF			0x07000
+#define	STX_CTRL_PERF_CNT		0x07008
+
+/* Safari/JBus error log register */
+#define	STX_CTRL_BUS_ERRLOG_BADCMD	0x4000000000000000ULL
+#define	SCZ_CTRL_BUS_ERRLOG_SSMDIS	0x2000000000000000ULL
+#define	SCZ_CTRL_BUS_ERRLOG_BADMA	0x1000000000000000ULL
+#define	SCZ_CTRL_BUS_ERRLOG_BADMB	0x0800000000000000ULL
+#define	SCZ_CTRL_BUS_ERRLOG_BADMC	0x0400000000000000ULL
+#define	TOM_CTRL_BUS_ERRLOG_SNOOP_GR	0x0000000000200000ULL
+#define	TOM_CTRL_BUS_ERRLOG_SNOOP_PCI	0x0000000000100000ULL
+#define	TOM_CTRL_BUS_ERRLOG_SNOOP_RD	0x0000000000080000ULL
+#define	TOM_CTRL_BUS_ERRLOG_SNOOP_RDS	0x0000000000020000ULL
+#define	TOM_CTRL_BUS_ERRLOG_SNOOP_RDSA	0x0000000000010000ULL
+#define	TOM_CTRL_BUS_ERRLOG_SNOOP_OWN	0x0000000000008000ULL
+#define	TOM_CTRL_BUS_ERRLOG_SNOOP_RDO	0x0000000000004000ULL
+#define	SCZ_CTRL_BUS_ERRLOG_CPU1PS	0x0000000000002000ULL
+#define	TOM_CTRL_BUS_ERRLOG_WDATA_PERR	0x0000000000002000ULL
+#define	SCZ_CTRL_BUS_ERRLOG_CPU1PB	0x0000000000001000ULL
+#define	TOM_CTRL_BUS_ERRLOG_CTRL_PERR	0x0000000000001000ULL
+#define	SCZ_CTRL_BUS_ERRLOG_CPU0PS	0x0000000000000800ULL
+#define	TOM_CTRL_BUS_ERRLOG_SNOOP_ERR	0x0000000000000800ULL
+#define	SCZ_CTRL_BUS_ERRLOG_CPU0PB	0x0000000000000400ULL
+#define	TOM_CTRL_BUS_ERRLOG_JBUS_ILL_B	0x0000000000000400ULL
+#define	SCZ_CTRL_BUS_ERRLOG_CIQTO	0x0000000000000200ULL
+#define	SCZ_CTRL_BUS_ERRLOG_LPQTO	0x0000000000000100ULL
+#define	TOM_CTRL_BUS_ERRLOG_JBUS_ILL_C	0x0000000000000100ULL
+#define	SCZ_CTRL_BUS_ERRLOG_SFPQTO	0x0000000000000080ULL
+#define	SCZ_CTRL_BUS_ERRLOG_UFPQTO	0x0000000000000040ULL
+#define	TOM_CTRL_BUS_ERRLOG_RD_PERR	0x0000000000000040ULL
+#define	STX_CTRL_BUS_ERRLOG_APERR	0x0000000000000020ULL
+#define	STX_CTRL_BUS_ERRLOG_UNMAP	0x0000000000000010ULL
+#define	STX_CTRL_BUS_ERRLOG_BUSERR	0x0000000000000004ULL
+#define	STX_CTRL_BUS_ERRLOG_TIMEOUT	0x0000000000000002ULL
+#define	SCZ_CTRL_BUS_ERRLOG_ILL		0x0000000000000001ULL
+
+/* ECC control register */
+#define	STX_CTRL_ECCCTRL_EE		0x8000000000000000ULL
+#define	STX_CTRL_ECCCTRL_UE		0x4000000000000000ULL
+#define	STX_CTRL_ECCCTRL_CE		0x2000000000000000ULL
+
+/* Uncorrectable error asynchronous fault status register */
+#define	STX_CTRL_UE_AFSR_P_PIO		0x8000000000000000ULL
+#define	STX_CTRL_UE_AFSR_P_DRD		0x4000000000000000ULL
+#define	STX_CTRL_UE_AFSR_P_DWR		0x2000000000000000ULL
+#define	STX_CTRL_UE_AFSR_S_PIO		0x1000000000000000ULL
+#define	STX_CTRL_UE_AFSR_S_DRD		0x0800000000000000ULL
+#define	STX_CTRL_UE_AFSR_S_DWR		0x0400000000000000ULL
+#define	STX_CTRL_UE_AFSR_ERRPNDG	0x0300000000000000ULL
+#define	STX_CTRL_UE_AFSR_BMASK		0x000003ff00000000ULL
+#define	STX_CTRL_UE_AFSR_QOFF		0x00000000c0000000ULL
+#define	STX_CTRL_UE_AFSR_AID		0x000000001f000000ULL
+#define	STX_CTRL_UE_AFSR_PARTIAL	0x0000000000800000ULL
+#define	STX_CTRL_UE_AFSR_OWNEDIN	0x0000000000400000ULL
+#define	STX_CTRL_UE_AFSR_MTAGSYND	0x00000000000f0000ULL
+#define	STX_CTRL_UE_AFSR_MTAG		0x000000000000e000ULL
+#define	STX_CTRL_UE_AFSR_ECCSYND	0x00000000000001ffULL
+
+/* Correctable error asynchronous fault status register */
+#define	STX_CTRL_CE_AFSR_P_PIO		0x8000000000000000ULL
+#define	STX_CTRL_CE_AFSR_P_DRD		0x4000000000000000ULL
+#define	STX_CTRL_CE_AFSR_P_DWR		0x2000000000000000ULL
+#define	STX_CTRL_CE_AFSR_S_PIO		0x1000000000000000ULL
+#define	STX_CTRL_CE_AFSR_S_DRD		0x0800000000000000ULL
+#define	STX_CTRL_CE_AFSR_S_DWR		0x0400000000000000ULL
+#define	STX_CTRL_CE_AFSR_ERRPNDG	0x0300000000000000ULL
+#define	STX_CTRL_CE_AFSR_BMASK		0x000003ff00000000ULL
+#define	STX_CTRL_CE_AFSR_QOFF		0x00000000c0000000ULL
+#define	STX_CTRL_CE_AFSR_AID		0x000000001f000000ULL
+#define	STX_CTRL_CE_AFSR_PARTIAL	0x0000000000800000ULL
+#define	STX_CTRL_CE_AFSR_OWNEDIN	0x0000000000400000ULL
+#define	STX_CTRL_CE_AFSR_MTAGSYND	0x00000000000f0000ULL
+#define	STX_CTRL_CE_AFSR_MTAG		0x000000000000e000ULL
+#define	STX_CTRL_CE_AFSR_ECCSYND	0x00000000000001ffULL
+
+/*
+ * Safari/JBus performance control register
+ * NB: for Tomatillo only events 0x00 through 0x08 are documented as
+ * implemented.
+ */
+#define	SCZ_CTRL_PERF_ZDATA_OUT		0x0000000000000016ULL
+#define	SCZ_CTRL_PERF_ZDATA_IN		0x0000000000000015ULL
+#define	SCZ_CTRL_PERF_ORQFULL		0x0000000000000014ULL
+#define	SCZ_CTRL_PERF_DVMA_WR		0x0000000000000013ULL
+#define	SCZ_CTRL_PERF_DVMA_RD		0x0000000000000012ULL
+#define	SCZ_CTRL_PERF_CYCPSESYS		0x0000000000000011ULL
+#define	STX_CTRL_PERF_PCI_B		0x000000000000000fULL
+#define	STX_CTRL_PERF_PCI_A		0x000000000000000eULL
+#define	STX_CTRL_PERF_UPA		0x000000000000000dULL
+#define	STX_CTRL_PERF_PIOINTRNL		0x000000000000000cULL
+#define	TOM_CTRL_PERF_WRI_WRIS		0x000000000000000bULL
+#define	STX_CTRL_PERF_INTRS		0x000000000000000aULL
+#define	STX_CTRL_PERF_PRTLWRMRGBUF	0x0000000000000009ULL
+#define	STX_CTRL_PERF_FGN_IO_HITS	0x0000000000000008ULL
+#define	STX_CTRL_PERF_FGN_IO_TRNS	0x0000000000000007ULL
+#define	STX_CTRL_PERF_OWN_CHRNT_HITS	0x0000000000000006ULL
+#define	STX_CTRL_PERF_OWN_CHRNT_TRNS	0x0000000000000005ULL
+#define	SCZ_CTRL_PERF_FGN_CHRNT_HITS	0x0000000000000004ULL
+#define	STX_CTRL_PERF_FGN_CHRNT_TRNS	0x0000000000000003ULL
+#define	STX_CTRL_PERF_CYCLES_PAUSE	0x0000000000000002ULL
+#define	STX_CTRL_PERF_BUSCYC		0x0000000000000001ULL
+#define	STX_CTRL_PERF_DIS		0x0000000000000000ULL
+#define	STX_CTRL_PERF_CNT1_SHIFT	11
+#define	STX_CTRL_PERF_CNT0_SHIFT	4
+
+/* Safari/JBus performance counter register */
+#define	STX_CTRL_PERF_CNT_MASK	0x00000000ffffffffULL
+#define	STX_CTRL_PERF_CNT_CNT1_SHIFT	32
+#define	STX_CTRL_PERF_CNT_CNT0_SHIFT	0
+
+/* INO defines */
+#define	STX_FB0_INO			0x2a	/* FB0 int. shared w/ UPA64s */
+#define	STX_FB1_INO			0x2b	/* FB1 int. shared w/ UPA64s */
+#define	STX_UE_INO			0x30	/* uncorrectable error */
+#define	STX_CE_INO			0x31	/* correctable error */
+#define	STX_PCIERR_A_INO		0x32	/* PCI bus A error */
+#define	STX_PCIERR_B_INO		0x33	/* PCI bus B error */
+#define	STX_BUS_INO			0x34	/* Safari/JBus error */
+#define	STX_MAX_INO			0x37
+
+/* Device space defines */
+#define	STX_CONF_SIZE			0x1000000
+#define	STX_CONF_BUS_SHIFT		16
+#define	STX_CONF_DEV_SHIFT		11
+#define	STX_CONF_FUNC_SHIFT		8
+#define	STX_CONF_REG_SHIFT		0
+#define	STX_IO_SIZE			0x1000000
+#define	STX_MEM_SIZE			0x100000000
+
+#define	STX_CONF_OFF(bus, slot, func, reg)				\
+	(((bus) << STX_CONF_BUS_SHIFT) |				\
+	((slot) << STX_CONF_DEV_SHIFT) |				\
+	((func) << STX_CONF_FUNC_SHIFT) |				\
+	((reg) << STX_CONF_REG_SHIFT))
+
+/* Definitions for the Schizo/Tomatillo configuration space */
+#define	STX_CS_DEVICE			0	/* bridge CS device number */
+#define	STX_CS_FUNC			0	/* brdige CS function number */
+
+/* Non-Standard registers in the configration space */
+/*
+ * NB: for Tomatillo the secondary and subordinate bus number registers
+ * apparently are read-only although documented otherwise; writing to
+ * them just triggers a PCI bus error interrupt or has no effect at best.
+ */
+#define	STX_CSR_SECBUS			0x40	/* secondary bus number */
+#define	STX_CSR_SUBBUS			0x41	/* subordinate bus number */
+
+/* Width of the physical addresses the IOMMU translates to */
+#define	STX_IOMMU_BITS			43
+
+#endif /* !_SPARC64_PCI_SCHIZOREG_H_ */
diff --git a/sys/sparc64/pci/schizovar.h b/sys/sparc64/pci/schizovar.h
new file mode 100644
index 0000000..39d25e6
--- /dev/null
+++ b/sys/sparc64/pci/schizovar.h
@@ -0,0 +1,71 @@
+/*-
+ * Copyright (c) 2005 by Marius Strobl <marius@FreeBSD.org>.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification, immediately at the beginning of the file.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _SPARC64_PCI_SCHIZOVAR_H_
+#define	_SPARC64_PCI_SCHIZOVAR_H_
+
+struct schizo_softc {
+	device_t			sc_dev;
+
+	struct mtx			*sc_mtx;
+
+	phandle_t			sc_node;
+
+	u_int				sc_mode;
+#define	SCHIZO_MODE_SCZ		1
+#define	SCHIZO_MODE_TOM		2
+#define	SCHIZO_MODE_XMS		3
+
+	u_int				sc_half;
+	uint32_t			sc_ign;
+	uint32_t			sc_ver;
+
+	struct resource			*sc_mem_res[TOM_NREG];
+	struct resource			*sc_irq_res[STX_NINTR];
+	void				*sc_ihand[STX_NINTR];
+
+	struct iommu_state		sc_is;
+
+	struct rman			sc_pci_mem_rman;
+	struct rman			sc_pci_io_rman;
+	bus_space_handle_t		sc_pci_bh[STX_NRANGE];
+	bus_space_tag_t			sc_pci_cfgt;
+	bus_space_tag_t			sc_pci_iot;
+	bus_space_tag_t			sc_pci_memt;
+	bus_dma_tag_t			sc_pci_dmat;
+
+	uint8_t				sc_pci_secbus;
+
+	struct ofw_bus_iinfo		sc_pci_iinfo;
+
+	SLIST_ENTRY(schizo_softc)	sc_link;
+};
+
+#endif /* !_SPARC64_PCI_SCHIZOVAR_H_ */