- Merge the *_SET macros from fire(4) which generally print out the

  register changes when compiled with SCHIZO_DEBUG and take advantage
  of them.
- Add support for the XMITS Fireplane/Safari to PCI-X bridges. I tought
  I'd need this for a Sun Fire 3800, which then turned out to not being
  equipped with such a bridge though. The support for these should be
  complete but given that it hasn't actually been tested probing is
  disabled for now.
  This required a way to alter the XMITS configuration in case a PCI-X
  device is found further down the device tree so the sparc64 specific
  ofw_pci kobj was revived with a ofw_pci_setup_device method, which is
  called by the ofw_pcibus code for every device added.
- A closer inspection of the OpenSolaris code indicates that consistent
  DMA flushing/syncing as well as the block store workaround should be
  applied with every BUS_DMASYNC_POSTREAD instead of in a wrapper around
  interrupt handlers for devices behind PCI-PCI bridges only as suggested
  by the documentation (code for the latter actually exists in OpenSolaris
  but is disabled by default), which also makes more sense.
- Add a workaround for Casinni/Skyhawk combinations. Chances are that
  this solves the crashes seen when using the the on-board Casinni NICs
  of Sun Fire V480 equipped with centerplanes other than 501-6780 or
  501-6790. This also takes advantage of the ofw_pci_setup_device method.
- Mark some unused parameters as such.

1 files changed, 36 insertions, 2 deletions

diff --git a/sys/sparc64/pci/schizoreg.h b/sys/sparc64/pci/schizoreg.h
index d538cd0..cd816b5 100644
--- a/sys/sparc64/pci/schizoreg.h
+++ b/sys/sparc64/pci/schizoreg.h
@@ -55,9 +55,13 @@
 #define	STX_PCI_AFSR			0x02010
 #define	STX_PCI_AFAR			0x02018
 #define	STX_PCI_DIAG			0x02020
+#define	XMS_PCI_PARITY_DETECT		0x02040
 #define	TOM_PCI_IOC_CSR			0x02248
 #define	TOM_PCI_IOC_TAG			0x02290
 #define	TOM_PCI_IOC_DATA		0x02290
+#define	XMS_PCI_X_ERR_STAT		0x02300
+#define	XMS_PCI_X_DIAG			0x02308
+#define	XMS_PCI_UPPER_RETRY_COUNTER	0x02310
 #define	STX_PCI_STRBUF			0x02800
 #define	STX_PCI_STRBUF_CTXFLUSH		0x02818
 #define	STX_PCI_IOMMU_SVADIAG		0x0a400
@@ -68,7 +72,7 @@
 #define	STX_PCI_IOBIO_DIAG		0x0a808
 #define	STX_PCI_STRBUF_CTXMATCH		0x10000
 
-/* PCI configuration/idle check diagnostic registers */
+/* PCI configuration/idle check diagnostic register */
 #define	SX_PCI_CFG_ICD_PCI_2_0_COMPAT	0x0000000000008000ULL
 #define	SX_PCI_CFG_ICD_DMAW_PERR_IEN	0x0000000000004000ULL
 #define	SX_PCI_CFG_ICD_IFC_NOT_IDLE	0x0000000000000010ULL
@@ -77,7 +81,7 @@
 #define	SX_PCI_CFG_ICD_PBM_NOT_IDLE	0x0000000000000002ULL
 #define	SX_PCI_CFG_ICD_STC_NOT_IDLE	0x0000000000000001ULL
 
-/* PCI IOMMU control registers */
+/* PCI IOMMU control register */
 #define	TOM_PCI_IOMMU_ERR_BAD_VA	0x0000000010000000ULL
 #define	TOM_PCI_IOMMU_ERR_ILLTSBTBW	0x0000000008000000ULL
 #define	TOM_PCI_IOMMU_ECC_ERR		0x0000000006000000ULL
@@ -94,6 +98,7 @@
 #define	TOM_PCI_CTRL_DTO_ERR		0x4000000000000000ULL
 #define	TOM_PCI_CTRL_DTO_IEN		0x2000000000000000ULL
 #define	SCZ_PCI_CTRL_ESLCK		0x0008000000000000ULL
+#define	XMS_PCI_CTRL_DMA_WR_PERR	0x0008000000000000ULL
 #define	SCZ_PCI_CTRL_ERRSLOT		0x0007000000000000ULL
 #define	STX_PCI_CTRL_TTO_ERR		0x0000004000000000ULL
 #define	STX_PCI_CTRL_RTRY_ERR		0x0000002000000000ULL
@@ -101,16 +106,19 @@
 #define	SCZ_PCI_CTRL_SBH_ERR		0x0000000800000000ULL
 #define	STX_PCI_CTRL_SERR		0x0000000400000000ULL
 #define	SCZ_PCI_CTRL_PCISPD		0x0000000200000000ULL
+#define	XMS_PCI_CTRL_X_MODE		0x0000000100000000ULL
 #define	TOM_PCI_CTRL_PRM		0x0000000040000000ULL
 #define	TOM_PCI_CTRL_PRO		0x0000000020000000ULL
 #define	TOM_PCI_CTRL_PRL		0x0000000010000000ULL
 #define	STX_PCI_CTRL_PTO		0x0000000003000000ULL
+#define	XMS_PCI_CTRL_X_ERRINT_EN	0x0000000000100000ULL
 #define	STX_PCI_CTRL_MMU_IEN		0x0000000000080000ULL
 #define	STX_PCI_CTRL_SBH_IEN		0x0000000000040000ULL
 #define	STX_PCI_CTRL_ERR_IEN		0x0000000000020000ULL
 #define	STX_PCI_CTRL_ARB_PARK		0x0000000000010000ULL
 #define	SCZ_PCI_CTRL_PCIRST		0x0000000000000100ULL
 #define	STX_PCI_CTRL_ARB_MASK		0x00000000000000ffULL
+#define	XMS_PCI_CTRL_XMITS10_ARB_MASK	0x000000000000000fULL
 
 /* PCI asynchronous fault status register */
 #define	STX_PCI_AFSR_P_MA		0x8000000000000000ULL
@@ -160,6 +168,32 @@
 #define	TOM_PCI_IOC_CPRO		0x0000000000000002ULL
 #define	TOM_PCI_IOC_CPRL		0x0000000000000001ULL
 
+/* XMITS PCI-X error status register */
+#define	XMS_PCI_X_ERR_STAT_P_SC_DSCRD	0x8000000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_P_SC_TTO	0x4000000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_P_SDSTAT	0x2000000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_P_SMMU	0x1000000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_P_CDSTAT	0x0800000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_P_CMMU	0x0400000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_S_SC_DSCRD	0x0080000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_S_SC_TTO	0x0040000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_S_SDSTAT	0x0020000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_S_SMMU	0x0010000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_S_CDSTAT	0x0008000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_S_CMMU	0x0004000000000000ULL
+#define	XMS_PCI_X_ERR_STAT_PERR_RCV_IEN	0x0000000400000000ULL
+#define	XMS_PCI_X_ERR_STAT_PERR_RCV	0x0000000200000000ULL
+#define	XMS_PCI_X_ERR_STAT_SERR_ON_PERR	0x0000000100000000ULL
+
+/* XMITS PCI-X diagnostic register */
+#define	XMS_PCI_X_DIAG_DIS_FAIR		0x0000000000080000ULL
+#define	XMS_PCI_X_DIAG_CRCQ_VALID	0x0000000000040000ULL
+#define	XMS_PCI_X_DIAG_SRCQ_ONE		0x0000000000000200ULL
+#define	XMS_PCI_X_DIAG_CRCQ_FLUSH	0x0000000000000100ULL
+#define	XMS_PCI_X_DIAG_BUGCNTL_MASK	0x0000ffff00000000ULL
+#define	XMS_PCI_X_DIAG_BUGCNTL_SHIFT	32
+#define	XMS_PCI_X_DIAG_SRCQ_MASK	0x00000000000000ffULL
+
 /* Controller configuration and status registers */
 /* Note that these are shared on Schizo but per-PBM on Tomatillo. */
 #define	STX_CTRL_BUS_ERRLOG		0x00018