Add SMP aware cache flushing functions, which operate on a single physical

page.  These send IPIs if necessary in order to keep the caches in sync on
all cpus.

2 files changed, 88 insertions, 15 deletions

diff --git a/sys/sparc64/include/cache.h b/sys/sparc64/include/cache.h
index 0ef20fe..1ebffc1 100644
--- a/sys/sparc64/include/cache.h
+++ b/sys/sparc64/include/cache.h
@@ -104,25 +104,48 @@ void	ecache_flush(vm_offset_t, vm_offset_t);
 void	ecache_inval_phys(vm_offset_t, vm_offset_t);
 #endif
 
+void	dcache_page_inval(vm_offset_t pa);
+void	icache_page_inval(vm_offset_t pa);
+
+#define	DC_TAG_SHIFT	2
+#define	DC_VALID_SHIFT	0
+
+#define	DC_TAG_BITS	28
+#define	DC_VALID_BITS	2
+
+#define	DC_TAG_MASK	((1 << DC_TAG_BITS) - 1)
+#define	DC_VALID_MASK	((1 << DC_VALID_BITS) - 1)
+
+#define	IC_TAG_SHIFT	7
+#define	IC_VALID_SHIFT	36
+
+#define	IC_TAG_BITS	28
+#define	IC_VALID_BITS	1
+
+#define	IC_TAG_MASK	((1 << IC_TAG_BITS) - 1)
+#define	IC_VALID_MASK	((1 << IC_VALID_BITS) - 1)
+
 /*
  * Cache control information.
  */
 struct cacheinfo {
-	int	c_enabled;		/* true => cache is enabled */
-	int 	ic_size;		/* instruction cache */
-	int	ic_set;
-	int	ic_l2set;
-	int 	ic_assoc;
-	int 	ic_linesize;
-	int 	dc_size;		/* data cache */
-	int	dc_l2size;
-	int 	dc_assoc;
-	int 	dc_linesize;
-	int	ec_size;		/* external cache info */
-	int 	ec_assoc;
-	int	ec_l2set;
-	int	ec_linesize;
-	int	ec_l2linesize;
+	u_int	c_enabled;		/* true => cache is enabled */
+	u_int 	ic_size;		/* instruction cache */
+	u_int	ic_set;
+	u_int	ic_l2set;
+	u_int 	ic_assoc;
+	u_int 	ic_linesize;
+	u_int 	dc_size;		/* data cache */
+	u_int	dc_l2size;
+	u_int 	dc_assoc;
+	u_int 	dc_linesize;
+	u_int	ec_size;		/* external cache info */
+	u_int 	ec_assoc;
+	u_int	ec_l2set;
+	u_int	ec_linesize;
+	u_int	ec_l2linesize;
 };
 
+extern struct cacheinfo cache;
+
 #endif	/* !_MACHINE_CACHE_H_ */
diff --git a/sys/sparc64/include/smp.h b/sys/sparc64/include/smp.h
index 958fa0c..03fbc04 100644
--- a/sys/sparc64/include/smp.h
+++ b/sys/sparc64/include/smp.h
@@ -57,6 +57,11 @@ struct cpu_start_args {
 	struct	tte csa_ttes[PCPU_PAGES];
 };
 
+struct ipi_cache_args {
+	u_int	ica_mask;
+	u_long	ica_pa;
+};
+
 struct ipi_tlb_args {
 	u_int	ita_mask;
 	u_long	ita_tlb;
@@ -80,6 +85,7 @@ void	ipi_all_but_self(u_int ipi);
 
 vm_offset_t mp_tramp_alloc(void);
 
+extern	struct	ipi_cache_args ipi_cache_args;
 extern	struct	ipi_level_args ipi_level_args;
 extern	struct	ipi_tlb_args ipi_tlb_args;
 
@@ -91,6 +97,8 @@ extern	u_long mp_tramp_func;
 
 extern	void mp_startup(void);
 
+extern	char tl_ipi_dcache_page_inval[];
+extern	char tl_ipi_icache_page_inval[];
 extern	char tl_ipi_level[];
 extern	char tl_ipi_test[];
 extern	char tl_ipi_tlb_context_demap[];
@@ -99,6 +107,36 @@ extern	char tl_ipi_tlb_range_demap[];
 
 #ifdef SMP
 
+static __inline void *
+ipi_dcache_page_inval(vm_offset_t pa)
+{
+	struct ipi_cache_args *ica;
+
+	if (smp_cpus == 1)
+		return (NULL);
+	ica = &ipi_cache_args;
+	ica->ica_mask = all_cpus;
+	ica->ica_pa = pa;
+	cpu_ipi_selected(all_cpus, 0, (u_long)tl_ipi_dcache_page_inval,
+	    (u_long)ica);
+	return (&ica->ica_mask);
+}
+
+static __inline void *
+ipi_icache_page_inval(vm_offset_t pa)
+{
+	struct ipi_cache_args *ica;
+
+	if (smp_cpus == 1)
+		return (NULL);
+	ica = &ipi_cache_args;
+	ica->ica_mask = all_cpus;
+	ica->ica_pa = pa;
+	cpu_ipi_selected(all_cpus, 0, (u_long)tl_ipi_icache_page_inval,
+	    (u_long)ica);
+	return (&ica->ica_mask);
+}
+
 #ifdef _MACHINE_PMAP_H_
 
 static __inline void *
@@ -174,6 +212,18 @@ ipi_wait(void *cookie)
 #else
 
 static __inline void *
+ipi_dcache_page_inval(vm_offset_t pa)
+{
+	return (NULL);
+}
+
+static __inline void *
+ipi_icache_page_inval(vm_offset_t pa)
+{
+	return (NULL);
+}
+
+static __inline void *
 ipi_tlb_context_demap(struct pmap *pm)
 {
 	return (NULL);