- Allow the front-end to specify that iommu(4) should disable

  rerun of the streaming cache for silicon bug workarounds.
- Announce the presence of a streaming cache on attach for
  informational purposes.
- For performance reasons don't do unnecessary flushes of the
  streaming cache when coherent mappings are synced.
- Fix some minor style issues.

2 files changed, 11 insertions, 7 deletions

diff --git a/sys/sparc64/include/iommureg.h b/sys/sparc64/include/iommureg.h
index 0218cfa..6032ac5 100644
--- a/sys/sparc64/include/iommureg.h
+++ b/sys/sparc64/include/iommureg.h
@@ -54,7 +54,7 @@
 #define	ISR_PGFLUSH	0x0008	/* streaming buffer page flush */
 #define	ISR_FLUSHSYNC	0x0010	/* streaming buffer flush sync */
 
-/* streaming buffer diagnostics registers. */
+/* streaming buffer diagnostics registers */
 #define	ISD_DATA_DIAG	0x0000	/* streaming buffer data RAM diag 0..127 */
 #define	ISD_ERROR_DIAG	0x0400	/* streaming buffer error status diag 0..127 */
 #define	ISD_PG_TAG_DIAG	0x0800	/* streaming buffer page tag diag 0..15 */
@@ -63,6 +63,7 @@
 /* streaming buffer control register */
 #define STRBUF_EN		0x0000000000000001UL
 #define STRBUF_D		0x0000000000000002UL
+#define STRBUF_RR_DIS		0x0000000000000004UL
 
 #define	IOMMU_MAXADDR(bits)	((1UL << (bits)) - 1)
 
@@ -91,7 +92,7 @@
 #define IOMMUCR_EN		0x0000000000000001UL
 
 /*
- * Diagnostic register definitions.
+ * Diagnostic register definitions
  */
 #define	IOMMU_DTAG_VPNBITS	19
 #define	IOMMU_DTAG_VPNMASK	((1 << IOMMU_DTAG_VPNBITS) - 1)
@@ -126,10 +127,10 @@
 /* Writeable */
 #define IOTTE_W			0x0000000000000002UL
 
-/* log2 of the IOMMU TTE size. */
+/* log2 of the IOMMU TTE size */
 #define	IOTTE_SHIFT		3
 
-/* Streaming buffer line size. */
+/* Streaming buffer line size */
 #define	STRBUF_LINESZ		64
 
 /*
diff --git a/sys/sparc64/include/iommuvar.h b/sys/sparc64/include/iommuvar.h
index 644a3fa..5904f04 100644
--- a/sys/sparc64/include/iommuvar.h
+++ b/sys/sparc64/include/iommuvar.h
@@ -45,12 +45,12 @@
 TAILQ_HEAD(iommu_maplruq_head, bus_dmamap);
 
 /*
- * Per-IOMMU state. The parenthesized comments indicate the locking strategy:
+ * Per-IOMMU state; the parenthesized comments indicate the locking strategy:
  *	i - protected by is_mtx.
  *	r - read-only after initialization.
  *	* - comment refers to pointer target / target hardware registers
  *	    (for bus_addr_t).
- * is_maplruq is also locked by is_mtx. Elements of is_tsb may only be
+ * is_maplruq is also locked by is_mtx.  Elements of is_tsb may only be
  * accessed from functions operating on the map owning the corresponding
  * resource, so the locking the user is required to do to protect the
  * map is sufficient.
@@ -81,7 +81,7 @@ struct iommu_state {
 	 */
 	volatile char		is_flush[STRBUF_FLUSHSYNC_NBYTES * 3 - 1];
 
-	/* copies of our parents state, to allow us to be self contained */
+	/* copies of our parent's state, to allow us to be self contained */
 	bus_space_tag_t		is_bustag;	/* (r) Our bus tag */
 	bus_space_handle_t	is_bushandle;	/* (r) */
 	bus_addr_t		is_iommu;	/* (r, *i) IOMMU registers */
@@ -96,6 +96,9 @@ struct iommu_state {
 	bus_addr_t		is_dva;		/* (r, *r) */
 	/* Tag compare diagnostics access */
 	bus_addr_t		is_dtcmp;	/* (r, *r) */
+	/* behavior flags */
+	u_int			is_flags;	/* (r) */
+#define	IOMMU_RERUN_DISABLE	(1 << 0)
 };
 
 /* interfaces for PCI/SBus code */