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| author | marius <marius@FreeBSD.org> | 2008-09-08 21:24:25 +0000 |
|---|---|---|
| committer | marius <marius@FreeBSD.org> | 2008-09-08 21:24:25 +0000 |
| commit | b484b97e7766f8d643ff205558ce5176240c6765 (patch) | |
| tree | 8de24e7dfb4d5986202a232027c3d33dc8601617 /sys/sparc64/include | |
| parent | 45e57c6bd280ab3f6744865db7ee4888c8b2e08b (diff) | |
| download | FreeBSD-src-b484b97e7766f8d643ff205558ce5176240c6765.zip FreeBSD-src-b484b97e7766f8d643ff205558ce5176240c6765.tar.gz | |
For cheetah-class CPUs ensure that the dt512_0 is set to hold 8k pages
for all three contexts and configure the dt512_1 to hold 4MB pages for
them (e.g. for direct mappings).
This might allow for additional optimization by using the faulting
page sizes provided by AA_DMMU_TAG_ACCESS_EXT for bypassing the page
size walker for the dt512 in the superpage support code.
Submitted by: nwhitehorn (initial patch)
Diffstat (limited to 'sys/sparc64/include')
| -rw-r--r-- | sys/sparc64/include/asi.h | 1 | ||||
| -rw-r--r-- | sys/sparc64/include/tlb.h | 31 |
2 files changed, 30 insertions, 2 deletions
diff --git a/sys/sparc64/include/asi.h b/sys/sparc64/include/asi.h index 7829de4..9371378 100644 --- a/sys/sparc64/include/asi.h +++ b/sys/sparc64/include/asi.h @@ -140,6 +140,7 @@ #define AA_DMMU_TSB_PEXT_REG 0x48 #define AA_DMMU_TSB_SEXT_REG 0x50 #define AA_DMMU_TSB_NEXT_REG 0x58 +#define AA_DMMU_TAG_ACCESS_EXT 0x60 /* US-III family */ #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a diff --git a/sys/sparc64/include/tlb.h b/sys/sparc64/include/tlb.h index 3d54ef8..06a8296 100644 --- a/sys/sparc64/include/tlb.h +++ b/sys/sparc64/include/tlb.h @@ -51,6 +51,34 @@ #define TLB_TAR_VA(va) ((va) & ~TAR_CTX_MASK) #define TLB_TAR_CTX(ctx) ((ctx) & TAR_CTX_MASK) +#define TLB_CXR_CTX_BITS (13) +#define TLB_CXR_CTX_MASK \ + (((1UL << TLB_CXR_CTX_BITS) - 1) << TLB_CXR_CTX_SHIFT) +#define TLB_CXR_CTX_SHIFT (0) +#define TLB_CXR_PGSZ_BITS (3) +#define TLB_PCXR_PGSZ_MASK \ + ((((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_N_PGSZ0_SHIFT) | \ + (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_N_PGSZ1_SHIFT) | \ + (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_P_PGSZ0_SHIFT) | \ + (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_PCXR_P_PGSZ1_SHIFT)) +#define TLB_PCXR_N_PGSZ0_SHIFT (61) +#define TLB_PCXR_N_PGSZ1_SHIFT (58) +#define TLB_PCXR_P_PGSZ0_SHIFT (16) +#define TLB_PCXR_P_PGSZ1_SHIFT (19) +#define TLB_SCXR_PGSZ_MASK \ + ((((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_SCXR_S_PGSZ0_SHIFT) | \ + (((1UL << TLB_CXR_PGSZ_BITS) - 1) << TLB_SCXR_S_PGSZ1_SHIFT)) +#define TLB_SCXR_S_PGSZ1_SHIFT (19) +#define TLB_SCXR_S_PGSZ0_SHIFT (16) + +#define TLB_TAE_PGSZ_BITS (3) +#define TLB_TAE_PGSZ0_MASK \ + (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ0_SHIFT) +#define TLB_TAE_PGSZ1_MASK \ + (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ1_SHIFT) +#define TLB_TAE_PGSZ0_SHIFT (16) +#define TLB_TAE_PGSZ1_SHIFT (19) + #define TLB_DEMAP_ID_SHIFT (4) #define TLB_DEMAP_ID_PRIMARY (0) #define TLB_DEMAP_ID_SECONDARY (1) @@ -59,8 +87,7 @@ #define TLB_DEMAP_TYPE_SHIFT (6) #define TLB_DEMAP_TYPE_PAGE (0) #define TLB_DEMAP_TYPE_CONTEXT (1) -/* US-III and greater only */ -#define TLB_DEMAP_TYPE_ALL (2) +#define TLB_DEMAP_TYPE_ALL (2) /* USIII and beyond only */ #define TLB_DEMAP_VA(va) ((va) & ~PAGE_MASK) #define TLB_DEMAP_ID(id) ((id) << TLB_DEMAP_ID_SHIFT) |
