cosmetic changes and style fixes

4 files changed, 25 insertions, 24 deletions

diff --git a/sys/sparc64/include/asi.h b/sys/sparc64/include/asi.h
index a05166f..7829de4 100644
--- a/sys/sparc64/include/asi.h
+++ b/sys/sparc64/include/asi.h
@@ -143,7 +143,7 @@
 
 #define	ASI_DMMU_TSB_8KB_PTR_REG		0x59
 #define	ASI_DMMU_TSB_64KB_PTR_REG		0x5a
-#define	ASI_DMMU_TSB_DIRECT_PTR_REG 		0x5b
+#define	ASI_DMMU_TSB_DIRECT_PTR_REG		0x5b
 #define	ASI_DTLB_DATA_IN_REG			0x5c
 /* US-III Cu: also ASI_DTLB_CAM_ADDRESS_REG */
 #define	ASI_DTLB_DATA_ACCESS_REG		0x5d
diff --git a/sys/sparc64/include/cache.h b/sys/sparc64/include/cache.h
index 9404554..c2c2b23 100644
--- a/sys/sparc64/include/cache.h
+++ b/sys/sparc64/include/cache.h
@@ -1,6 +1,6 @@
 /*-
  * Copyright (c) 1996
- * 	The President and Fellows of Harvard College. All rights reserved.
+ *	The President and Fellows of Harvard College. All rights reserved.
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
  *
@@ -43,7 +43,7 @@
  */
 
 #ifndef _MACHINE_CACHE_H_
-#define _MACHINE_CACHE_H_
+#define	_MACHINE_CACHE_H_
 
 #ifndef LOCORE
 #include <dev/ofw/openfirm.h>
@@ -77,21 +77,21 @@
 #ifndef LOCORE
 
 /*
- * Cache control information.
+ * Cache control information
  */
 struct cacheinfo {
 	u_int	c_enabled;		/* true => cache is enabled */
-	u_int 	ic_size;		/* instruction cache */
+	u_int	ic_size;		/* instruction cache */
 	u_int	ic_set;
 	u_int	ic_l2set;
-	u_int 	ic_assoc;
-	u_int 	ic_linesize;
-	u_int 	dc_size;		/* data cache */
+	u_int	ic_assoc;
+	u_int	ic_linesize;
+	u_int	dc_size;		/* data cache */
 	u_int	dc_l2size;
-	u_int 	dc_assoc;
-	u_int 	dc_linesize;
+	u_int	dc_assoc;
+	u_int	dc_linesize;
 	u_int	ec_size;		/* external cache info */
-	u_int 	ec_assoc;
+	u_int	ec_assoc;
 	u_int	ec_l2set;
 	u_int	ec_linesize;
 	u_int	ec_l2linesize;
diff --git a/sys/sparc64/include/cpufunc.h b/sys/sparc64/include/cpufunc.h
index 211eec3..fca87e5 100644
--- a/sys/sparc64/include/cpufunc.h
+++ b/sys/sparc64/include/cpufunc.h
@@ -35,7 +35,7 @@
 struct thread;
 
 /*
- * membar operand macros for use in other macros when # is a special
+ * Membar operand macros for use in other macros when # is a special
  * character.  Keep these in sync with what the hardware expects.
  */
 #define	C_Lookaside	(0)
@@ -88,8 +88,8 @@ struct thread;
 	__asm __volatile("mov %0, %" __XSTRING(reg) : : "r" (val));	\
 } while (0)
 
-/* Generate ld*a/st*a functions for non-constant ASI's. */
-#define LDNC_GEN(tp, o)							\
+/* Generate ld*a/st*a functions for non-constant ASIs. */
+#define	LDNC_GEN(tp, o)							\
 	static __inline tp						\
 	o ## _nc(caddr_t va, int asi)					\
 	{								\
@@ -116,7 +116,7 @@ LDNC_GEN(u_long, ldxa);
 #define	lduwa(va, asi)	LD_GENERIC(va, asi, lduwa, u_int)
 #define	ldxa(va, asi)	LD_GENERIC(va, asi, ldxa, u_long)
 
-#define STNC_GEN(tp, o)							\
+#define	STNC_GEN(tp, o)							\
 	static __inline void						\
 	o ## _nc(caddr_t va, int asi, tp val)				\
 	{								\
@@ -175,9 +175,9 @@ int fasword32(u_long asi, void *addr, uint32_t *val);
 
 /*
  * Macro intended to be used instead of wr(asr23, val, xor) for writing to
- * the TICK_CMPR register in order to avoid a bug in BlackBird CPUs that
+ * the TICK_COMPARE register in order to avoid a bug in BlackBird CPUs that
  * can cause these writes to fail under certain condidtions which in turn
- * causes the hardclock to stop. The workaround is to perform the write
+ * causes the hardclock to stop.  The workaround is to perform the write
  * at the beginning of an I-Cache line directly followed by a dummy read.
  */
 #define	wrtickcmpr(val, xor) ({						\
@@ -193,13 +193,14 @@ int fasword32(u_long asi, void *addr, uint32_t *val);
 static __inline void
 breakpoint(void)
 {
+
 	__asm __volatile("ta %%xcc, 1" : :);
 }
 
 static __inline register_t
 intr_disable(void)
 {
-	u_long s;
+	register_t s;
 
 	s = rdpr(pstate);
 	wrpr(pstate, s & ~PSTATE_IE, 0);
@@ -209,11 +210,11 @@ intr_disable(void)
 
 /*
  * In some places, it is required that the store is directly followed by a
- * membar #Sync. Don't trust the compiler to not insert instructions in
- * between. We also need to disable interrupts completely.
+ * membar #Sync.  Don't trust the compiler to not insert instructions in
+ * between.  We also need to disable interrupts completely.
  */
 #define	stxa_sync(va, asi, val) do {					\
-	u_long s;							\
+	register_t s;							\
 	s = intr_disable();						\
 	__asm __volatile("stxa %0, [%1] %2; membar #Sync"		\
 	    : : "r" (val), "r" (va), "n" (asi));			\
@@ -226,7 +227,7 @@ void ascopyto(caddr_t src, u_long dasi, vm_offset_t dst, size_t len);
 void aszero(u_long asi, vm_offset_t dst, size_t len);
 
 /*
- * Ultrasparc II doesn't implement popc in hardware.  Suck.
+ * Ultrasparc II doesn't implement popc in hardware.
  */
 #if 0
 #define	HAVE_INLINE_FFS
diff --git a/sys/sparc64/include/pcpu.h b/sys/sparc64/include/pcpu.h
index f3a9f64..04f5ee6 100644
--- a/sys/sparc64/include/pcpu.h
+++ b/sys/sparc64/include/pcpu.h
@@ -49,11 +49,11 @@ struct pmap;
 	struct	intr_request *pc_irhead;				\
 	struct	intr_request **pc_irtail;				\
 	struct	intr_request *pc_irfree;				\
-	struct 	pmap *pc_pmap;						\
+	struct	pmap *pc_pmap;						\
 	vm_offset_t pc_addr;						\
 	u_long	pc_tickref;						\
 	u_long	pc_tickadj;						\
-	u_int 	pc_mid;							\
+	u_int	pc_mid;							\
 	u_int	pc_node;						\
 	u_int	pc_tlb_ctx;						\
 	u_int	pc_tlb_ctx_max;						\