- For Cheetah- and Zeus-class CPUs don't flush all unlocked entries from

  the TLBs in order to get rid of the user mappings but instead traverse
  them an flush only the latter like we also do for the Spitfire-class.
  Also flushing the unlocked kernel entries can cause instant faults which
  when called from within cpu_switch() are handled with the scheduler lock
  held which in turn can cause timeouts on the acquisition of the lock by
  other CPUs. This was easily seen with a 16-core V890 but occasionally
  also happened with 2-way machines.
  While at it, move the SPARC64-V support code entirely to zeus.c. This
  causes a little bit of duplication but is less confusing than partially
  using Cheetah-class bits for these.
- For SPARC64-V ensure that 4-Mbyte page entries are stored in the 1024-
  entry, 2-way set associative TLB.
- In {d,i}tlb_get_data_sun4u() turn off the interrupts in order to ensure
  that ASI_{D,I}TLB_DATA_ACCESS_REG actually are read twice back-to-back.

Tested by:      Peter Jeremy (16-core US-IV), Michael Moll (2-way SPARC64-V)

1 files changed, 14 insertions, 1 deletions

diff --git a/sys/sparc64/include/tlb.h b/sys/sparc64/include/tlb.h
index b813b0f..3f2c3c5 100644
--- a/sys/sparc64/include/tlb.h
+++ b/sys/sparc64/include/tlb.h
@@ -44,7 +44,17 @@
 	(TD_V | TD_4M | (TLB_DIRECT_ADDRESS_MASK - TLB_DIRECT_PAGE_MASK))
 
 #define	TLB_DAR_SLOT_SHIFT		(3)
-#define	TLB_DAR_SLOT(slot)		((slot) << TLB_DAR_SLOT_SHIFT)
+#define	TLB_DAR_TLB_SHIFT		(16)
+#define	TLB_DAR_SLOT(tlb, slot)						\
+	((tlb) << TLB_DAR_TLB_SHIFT | (slot) << TLB_DAR_SLOT_SHIFT)
+#define	TLB_DAR_T16			(0)	/* US-III{,i,+}, IV{,+} */
+#define	TLB_DAR_T32			(0)	/* US-I, II{,e,i} */
+#define	TLB_DAR_DT512_0			(2)	/* US-III{,i,+}, IV{,+} */
+#define	TLB_DAR_DT512_1			(3)	/* US-III{,i,+}, IV{,+} */
+#define	TLB_DAR_IT128			(2)	/* US-III{,i,+}, IV */
+#define	TLB_DAR_IT512			(2)	/* US-IV+ */
+#define	TLB_DAR_FTLB			(0)	/* SPARC64 V, VI, VII, VIIIfx */
+#define	TLB_DAR_STLB			(2)	/* SPARC64 V, VI, VII, VIIIfx */
 
 #define	TAR_VPN_SHIFT			(13)
 #define	TAR_CTX_MASK			((1 << TAR_VPN_SHIFT) - 1)
@@ -156,6 +166,9 @@ tlb_flush_user_t cheetah_tlb_flush_user;
 tlb_flush_nonlocked_t spitfire_tlb_flush_nonlocked;
 tlb_flush_user_t spitfire_tlb_flush_user;
 
+tlb_flush_nonlocked_t zeus_tlb_flush_nonlocked;
+tlb_flush_user_t zeus_tlb_flush_user;
+
 extern tlb_flush_nonlocked_t *tlb_flush_nonlocked;
 extern tlb_flush_user_t *tlb_flush_user;