Add initial smp support. This gets as far as allowing the secondary

cpu(s) into the kernel, and sync-ing them up to "kernel" mode so we can
send them ipis, which also work.

Thanks to John Baldwin for providing me with access to the hardware
that made this possible.

Parts obtained from:	bsd/os

1 files changed, 156 insertions, 0 deletions

diff --git a/sys/sparc64/include/smp.h b/sys/sparc64/include/smp.h
index 57a0f87..d97e191 100644
--- a/sys/sparc64/include/smp.h
+++ b/sys/sparc64/include/smp.h
@@ -29,4 +29,160 @@
 #ifndef	_MACHINE_SMP_H_
 #define	_MACHINE_SMP_H_
 
+#include <machine/intr_machdep.h>
+
+#define	CPU_INITING		1
+#define	CPU_INITED		2
+#define	CPU_REJECT		3
+#define	CPU_STARTING		4
+#define	CPU_STARTED		5
+#define	CPU_BOOTSTRAPING	6
+#define	CPU_BOOTSTRAPPED	7
+
+#ifndef	LOCORE
+
+#define	IDR_BUSY	(1<<0)
+#define	IDR_NACK	(1<<1)
+
+#define	IPI_AST		PIL_AST
+#define	IPI_RENDEZVOUS	PIL_RENDEZVOUS
+#define	IPI_STOP	PIL_STOP
+
+#define	IPI_RETRIES	100
+
+struct cpu_start_args {
+	u_int	csa_mid;
+	u_int	csa_state;
+	u_long	csa_data;
+	vm_offset_t csa_va;
+};
+
+struct ipi_level_args {
+	u_int	ila_count;
+	u_int	ila_level;
+};
+
+struct ipi_tlb_args {
+	u_int	ita_count;
+	u_long	ita_tlb;
+	u_long	ita_ctx;
+	u_long	ita_start;
+	u_long	ita_end;
+};
+#define	ita_va	ita_start
+
+struct pcpu;
+
+void	cpu_mp_bootstrap(struct pcpu *pc);
+
+void	cpu_ipi_selected(u_int cpus, u_long d0, u_long d1, u_long d2);
+void	cpu_ipi_send(u_int mid, u_long d0, u_long d1, u_long d2);
+
+void	ipi_selected(u_int cpus, u_int ipi);
+void	ipi_all(u_int ipi);
+void	ipi_all_but_self(u_int ipi);
+
+struct	ipi_level_args ipi_level_args;
+struct	ipi_tlb_args ipi_tlb_args;
+
+extern	int mp_ncpus;
+
+extern	char tl_ipi_level[];
+extern	char tl_ipi_test[];
+extern	char tl_ipi_tlb_context_demap[];
+extern	char tl_ipi_tlb_page_demap[];
+extern	char tl_ipi_tlb_range_demap[];
+
+#ifdef SMP
+
+static __inline void *
+ipi_tlb_context_demap(u_int ctx)
+{
+	struct ipi_tlb_args *ita;
+
+	if (mp_ncpus == 1)
+		return (NULL);
+	ita = &ipi_tlb_args;
+	ita->ita_count = mp_ncpus;
+	ita->ita_ctx = ctx;
+	cpu_ipi_selected(PCPU_GET(other_cpus), 0,
+	    (u_long)tl_ipi_tlb_context_demap, (u_long)ita);
+	return (&ita->ita_count);
+}
+
+static __inline void *
+ipi_tlb_page_demap(u_int tlb, u_int ctx, vm_offset_t va)
+{
+	struct ipi_tlb_args *ita;
+
+	if (mp_ncpus == 1)
+		return (NULL);
+	ita = &ipi_tlb_args;
+	ita->ita_count = mp_ncpus;
+	ita->ita_tlb = tlb;
+	ita->ita_ctx = ctx;
+	ita->ita_va = va;
+	cpu_ipi_selected(PCPU_GET(other_cpus), 0,
+	    (u_long)tl_ipi_tlb_page_demap, (u_long)ita);
+	return (&ita->ita_count);
+}
+
+static __inline void *
+ipi_tlb_range_demap(u_int ctx, vm_offset_t start, vm_offset_t end)
+{
+	struct ipi_tlb_args *ita;
+
+	if (mp_ncpus == 1)
+		return (NULL);
+	ita = &ipi_tlb_args;
+	ita->ita_count = mp_ncpus;
+	ita->ita_ctx = ctx;
+	ita->ita_start = start;
+	ita->ita_end = end;
+	cpu_ipi_selected(PCPU_GET(other_cpus), 0,
+	    (u_long)tl_ipi_tlb_range_demap, (u_long)ita);
+	return (&ita->ita_count);
+}
+
+static __inline void
+ipi_wait(void *cookie)
+{
+	u_int *count;
+
+	if ((count = cookie) != NULL) {
+		atomic_subtract_int(count, 1);
+		while (*count != 0)
+			membar(LoadStore);
+	}
+}
+
+#else
+
+static __inline void *
+ipi_tlb_context_demap(u_int ctx)
+{
+	return (NULL);
+}
+
+static __inline void *
+ipi_tlb_page_demap(u_int tlb, u_int ctx, vm_offset_t va)
+{
+	return (NULL);
+}
+
+static __inline void *
+ipi_tlb_range_demap(u_int ctx, vm_offset_t start, vm_offset_t end)
+{
+	return (NULL);
+}
+
+static __inline void
+ipi_wait(void *cookie)
+{
+}
+
+#endif /* SMP */
+
+#endif /* !LOCORE */
+
 #endif /* !_MACHINE_SMP_H_ */