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| author | nwhitehorn <nwhitehorn@FreeBSD.org> | 2008-09-22 03:21:02 +0000 |
|---|---|---|
| committer | nwhitehorn <nwhitehorn@FreeBSD.org> | 2008-09-22 03:21:02 +0000 |
| commit | 455aa296ae81bfbe41da8d580502213802c40940 (patch) | |
| tree | edf842c473de3e66dc90c90fb199f958023819c4 /sys/powerpc | |
| parent | ee5f77b812d5c9e28fbc019af3945d8b98a9d92d (diff) | |
| download | FreeBSD-src-455aa296ae81bfbe41da8d580502213802c40940.zip FreeBSD-src-455aa296ae81bfbe41da8d580502213802c40940.tar.gz | |
Unbreak G3 support. G3 processors don't have an L3 cache, so we shouldn't try to program it.
Approved by: marcel (mentor)
Diffstat (limited to 'sys/powerpc')
| -rw-r--r-- | sys/powerpc/powerpc/cpu.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/sys/powerpc/powerpc/cpu.c b/sys/powerpc/powerpc/cpu.c index e2a4f71..4abeb87 100644 --- a/sys/powerpc/powerpc/cpu.c +++ b/sys/powerpc/powerpc/cpu.c @@ -251,8 +251,6 @@ cpu_setup(u_int cpuid) } switch (vers) { - case MPC750: - case IBM750FX: case MPC7400: case MPC7410: case MPC7447A: @@ -260,11 +258,18 @@ cpu_setup(u_int cpuid) case MPC7450: case MPC7455: case MPC7457: + /* G3 systems don't have an L3 cache, so only check + * for G4 and above */ + + l3cr_config = mfspr(SPR_L3CR); + + /* Fallthrough */ + case MPC750: + case IBM750FX: cpu_print_speed(); printf("\n"); l2cr_config = mfspr(SPR_L2CR); - l3cr_config = mfspr(SPR_L3CR); if (bootverbose) cpu_print_cacheinfo(cpuid, vers); |
