- Update spr.h

- Add hid.h

Obtained from:	NetBSD

NOTE: This undoes some changes I'd made to prefix the processor name defines
with PVR_.  This was due to my original decision to use MPC750 as a cpu name.
With this changed, the PVR_ change is no longer required.

2 files changed, 325 insertions, 79 deletions

diff --git a/sys/powerpc/include/hid.h b/sys/powerpc/include/hid.h
new file mode 100644
index 0000000..ef23fd9
--- /dev/null
+++ b/sys/powerpc/include/hid.h
@@ -0,0 +1,129 @@
+/*-
+ * Copyright (c) 2000 Tsubai Masanari.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $NetBSD: hid.h,v 1.2 2001/08/22 21:05:25 matt Exp $
+ * $FreeBSD$
+ */
+
+#ifndef _POWERPC_HID_H_
+#define _POWERPC_HID_H_
+
+/* Hardware Implementation Dependent registers for the PowerPC */
+
+#define HID0_EMCP	0x80000000  /* Enable MCP */
+#define HID0_DBP	0x40000000  /* Disable 60x bus parity generation */
+#define HID0_EBA	0x20000000  /* Enable 60x bus address parity checking */
+#define HID0_EBD	0x10000000  /* Enable 60x bus data parity checking */
+#define HID0_BCLK	0x08000000  /* CLK_OUT clock type selection */
+#define HID0_EICE	0x04000000  /* Enable ICE output */
+#define HID0_TBEN	0x04000000  /* Time base enable (7450) */
+#define HID0_ECLK	0x02000000  /* CLK_OUT clock type selection */
+#define HID0_PAR	0x01000000  /* Disable precharge of ARTRY */
+#define HID0_STEN	0x01000000  /* Software table search enable (7450) */
+#define HID0_DOZE	0x00800000  /* Enable doze mode */
+#define HID0_NAP	0x00400000  /* Enable nap mode */
+#define HID0_SLEEP	0x00200000  /* Enable sleep mode */
+#define HID0_DPM	0x00100000  /* Enable Dynamic power management */
+#define HID0_RISEG	0x00080000  /* Read I-SEG */
+#define HID0_BHTCLR	0x00080000  /* Clear branch history table (7450) */
+#define HID0_EIEC	0x00040000  /* Enable internal error checking */
+#define HID0_XAEN	0x00040000  /* Enable eXtended Addressing (7450) */
+#define HID0_NHR	0x00010000  /* Not hard reset */
+#define HID0_ICE	0x00008000  /* Enable i-cache */
+#define HID0_DCE	0x00004000  /* Enable d-cache */
+#define HID0_ILOCK	0x00002000  /* i-cache lock */
+#define HID0_DLOCK	0x00001000  /* d-cache lock */
+#define HID0_ICFI	0x00000800  /* i-cache flush invalidate */
+#define HID0_DCFI	0x00000400  /* d-cache flush invalidate */
+#define HID0_SPD	0x00000200  /* Disable speculative cache access */
+#define HID0_IFEM	0x00000100  /* Enable M-bit for I-fetch */
+#define HID0_SGE	0x00000080  /* Enable store gathering */
+#define HID0_DCFA	0x00000040  /* Data cache flush assist */
+#define HID0_BTIC	0x00000020  /* Enable BTIC */
+#define HID0_ABE	0x00000008  /* Enable address broadcast */
+#define HID0_BHT	0x00000004  /* Enable branch history table */
+#define HID0_NOPTI	0x00000001  /* No-op the dcbt(st) */
+
+#define HID0_BITMASK							\
+    "\20"								\
+    "\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR"	\
+    "\030DOZE\027NAP\026SLEEP\025DPM\024RISEG\023EIEC\022res\021NHR"	\
+    "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011IFEM"	\
+    "\010SGE\007DCFA\006BTIC\005FBIOB\004ABE\003BHT\002NOPDST\001NOPTI"
+
+#define HID0_7450_BITMASK						\
+    "\20"								\
+    "\040EMCP\037b1\036b2\035b3\034b4\033TBEN\032b6\031STEN"		\
+    "\030b8\027NAP\026SLEEP\025DPM\024b12\023BHTCLR\022XAEN\021NHR"	\
+    "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011b23"	\
+    "\010SGE\007b25\006BTIC\005LRSTK\004FOLD\003BHT\002NOPDST\001NOPTI"
+
+/*
+ *  HID0 bit definitions per cpu model
+ *
+ * bit	603	604	750	7400	7410	7450
+ *   0	EMCP	EMCP	EMCP	EMCP	EMCP	-
+ *   1	-	ECP	DBP	-	-	-
+ *   2	EBA	EBA	EBA	EBA	EDA	-
+ *   3	EBD	EBD	EBD	EBD	EBD	-
+ *   4	SBCLK	-	BCLK	BCKL	BCLK	-
+ *   5	EICE	-	-	-	-	TBEN
+ *   6	ECLK	-	ECLK	ECLK	ECLK	-
+ *   7	PAR	PAR	PAR	PAR	PAR	STEN
+ *   8	DOZE	-	DOZE	DOZE	DOZE	-
+ *   9	NAP	-	NAP	NAP	NAP	NAP
+ *  10	SLEEP	-	SLEEP	SLEEP	SLEEP	SLEEP
+ *  11	DPM	-	DPM	DPM	DPM	DPM
+ *  12	RISEG	-	-	RISEG	-	-
+ *  13	-	-	-	EIEC	EIEC	BHTCLR
+ *  14	-	-	-	-	-	XAEN
+ *  15	-	NHR	NHR	NHR	NHR	NHR
+ *  16	ICE	ICE	ICE	ICE	ICE	ICE
+ *  17	DCE	DCE	DCE	DCE	DCE	DCE
+ *  18	ILOCK	ILOCK	ILOCK	ILOCK	ILOCK	ILOCK
+ *  19	DLOCK	DLOCK	DLOCK	DLOCK	DLOCK	DLOCK
+ *  20	ICFI	ICFI	ICFI	ICFI	ICFI	ICFI
+ *  21	DCFI	DCFI	DCFI	DCFI	DCFI	DCFI
+ *  22	-	-	SPD	SPD	SPG	SPD
+ *  23	-	-	IFEM	IFTT	IFTT	-
+ *  24	-	SIE	SGE	SGE	SGE	SGE
+ *  25	-	-	DCFA	DCFA	DCFA	-
+ *  26	-	-	BTIC	BTIC	BTIC	BTIC
+ *  27	FBIOB	-	-	-	-	LRSTK
+ *  28	-	-	ABE	-	-	FOLD
+ *  29	-	BHT	BHT	BHT	BHT	BHT
+ *  30	-	-	-	NOPDST	NOPDST	NOPDST
+ *  31	NOOPTI	-	NOOPTI	NOPTI	NOPTI	NOPTI
+ *
+ *  604: ECP = Enable cache parity checking
+ *  604: SIE = Serial instruction execution disable
+ * 7450: TBEN = Time Base Enable
+ * 7450: STEN = Software table lookup enable
+ * 7450: BHTCLR = Branch history clear
+ * 7450: LRSTK = Link Register Stack Enable
+ * 7450: FOLD = Branch folding enable
+ */
+
+#endif /* _POWERPC_HID_H_ */
diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h
index 02ef4b4..3eacd2f 100644
--- a/sys/powerpc/include/spr.h
+++ b/sys/powerpc/include/spr.h
@@ -30,6 +30,7 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
+ * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $
  * $FreeBSD$
  */
 #ifndef _POWERPC_SPR_H_
@@ -39,7 +40,7 @@
 #define	mtspr(reg, val)							\
 	__asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
 #define	mfspr(reg)							\
-	( { u_int32_t val;						\
+	( { register_t val;						\
 	  __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg));	\
 	  val; } )
 #endif /* _LOCORE */
@@ -74,7 +75,11 @@
 #define	SPR_SDR1		0x019	/* .68 Page table base address register */
 #define	SPR_SRR0		0x01a	/* 468 Save/Restore Register 0 */
 #define	SPR_SRR1		0x01b	/* 468 Save/Restore Register 1 */
+#define SPR_EIE			0x050	/* ..8 Exception Interrupt ??? */
+#define SPR_EID			0x051	/* ..8 Exception Interrupt ??? */
+#define SPR_NRI			0x052	/* ..8 Exception Interrupt ??? */
 #define	SPR_USPRG0		0x100	/* 4.. User SPR General 0 */
+#define	SPR_VRSAVE		0x100	/* .6. AltiVec VRSAVE */
 #define	SPR_SPRG0		0x110	/* 468 SPR General 0 */
 #define	SPR_SPRG1		0x111	/* 468 SPR General 1 */
 #define	SPR_SPRG2		0x112	/* 468 SPR General 2 */
@@ -83,59 +88,156 @@
 #define	SPR_SPRG5		0x115	/* 4.. SPR General 5 */
 #define	SPR_SPRG6		0x116	/* 4.. SPR General 6 */
 #define	SPR_SPRG7		0x117	/* 4.. SPR General 7 */
+#define	SPR_ASR			0x118	/* ... Address Space Register (PPC64) */
 #define	SPR_EAR			0x11a	/* .68 External Access Register */
 #define	SPR_TBL			0x11c	/* 468 Time Base Lower */
 #define	SPR_TBU			0x11d	/* 468 Time Base Upper */
 #define	SPR_PVR			0x11f	/* 468 Processor Version Register */
-#define   PVR_MPC601		  0x0001
-#define   PVR_MPC603		  0x0003
-#define   PVR_MPC604		  0x0004
-#define   PVR_MPC602		  0x0005
-#define   PVR_MPC603e		  0x0006
-#define   PVR_MPC603ev		  0x0007
-#define   PVR_MPC750		  0x0008
-#define   PVR_MPC604ev		  0x0009
-#define   PVR_MPC7400		  0x000c
-#define   PVR_MPC620		  0x0014
-#define   PVR_MPC860		  0x0050
-#define   PVR_MPC8240		  0x0081
-#define   PVR_MPC7450		  0x8000
-#define   PVR_MPC7455		  0x8001
-#define   PVR_MPC7410		  0x800c
-#define   PVR_IBM405GP		  0x4011
-#define   PVR_IBM405L		  0x4161
+#define	  MPC601		  0x0001
+#define	  MPC603		  0x0003
+#define	  MPC604		  0x0004
+#define	  MPC602		  0x0005
+#define	  MPC603e		  0x0006
+#define	  MPC603ev		  0x0007
+#define	  MPC750		  0x0008
+#define	  MPC604ev		  0x0009
+#define	  MPC7400		  0x000c
+#define	  MPC620		  0x0014
+#define	  IBM403		  0x0020
+#define	  IBM401A1		  0x0021
+#define	  IBM401B2		  0x0022
+#define	  IBM401C2		  0x0023
+#define	  IBM401D2		  0x0024
+#define	  IBM401E2		  0x0025
+#define	  IBM401F2		  0x0026
+#define	  IBM401G2		  0x0027
+#define	  IBMPOWER3		  0x0041
+#define	  MPC860		  0x0050
+#define	  MPC8240		  0x0081
+#define	  IBM405GP		  0x4011
+#define	  IBM405L		  0x4161
+#define	  IBM750FX		  0x7000
+#define	  MPC7450		  0x8000
+#define	  MPC7455		  0x8001
+#define	  MPC7410		  0x800c
+#define	  MPC8245		  0x8081
+
 #define	SPR_IBAT0U		0x210	/* .68 Instruction BAT Reg 0 Upper */
-#define	SPR_IBAT0L		0x211	/* .68 Instruction BAT Reg 0 Lower */
-#define	SPR_IBAT1U		0x212	/* .68 Instruction BAT Reg 1 Upper */
-#define	SPR_IBAT1L		0x213	/* .68 Instruction BAT Reg 1 Lower */
-#define	SPR_IBAT2U		0x214	/* .68 Instruction BAT Reg 2 Upper */
-#define	SPR_IBAT2L		0x215	/* .68 Instruction BAT Reg 2 Lower */
-#define	SPR_IBAT3U		0x216	/* .68 Instruction BAT Reg 3 Upper */
-#define	SPR_IBAT3L		0x217	/* .68 Instruction BAT Reg 3 Lower */
-#define	SPR_DBAT0U		0x218	/* .68 Data BAT Reg 0 Upper */
-#define	SPR_DBAT0L		0x219	/* .68 Data BAT Reg 0 Lower */
-#define	SPR_DBAT1U		0x21a	/* .68 Data BAT Reg 1 Upper */
-#define	SPR_DBAT1L		0x21b	/* .68 Data BAT Reg 1 Lower */
-#define	SPR_DBAT2U		0x21c	/* .68 Data BAT Reg 2 Upper */
-#define	SPR_DBAT2L		0x21d	/* .68 Data BAT Reg 2 Lower */
-#define	SPR_DBAT3U		0x21e	/* .68 Data BAT Reg 3 Upper */
-#define	SPR_DBAT3L		0x21f	/* .68 Data BAT Reg 3 Lower */
-#define	SPI_IBAT4U		0x230	/* .6. Instruction BAT Reg 4 Upper */
-#define	SPI_IBAT4L		0x231	/* .6. Instruction BAT Reg 4 Lower */
-#define	SPI_IBAT5U		0x232	/* .6. Instruction BAT Reg 5 Upper */
-#define	SPI_IBAT5L		0x233	/* .6. Instruction BAT Reg 5 Lower */
-#define	SPI_IBAT6U		0x234	/* .6. Instruction BAT Reg 6 Upper */
-#define	SPI_IBAT6L		0x235	/* .6. Instruction BAT Reg 6 Lower */
-#define	SPI_IBAT7U		0x236	/* .6. Instruction BAT Reg 7 Upper */
-#define	SPI_IBAT7L		0x237	/* .6. Instruction BAT Reg 7 Lower */
-#define	SPI_DBAT4U		0x238	/* .6. Data BAT Reg 4 Upper */
-#define	SPI_DBAT4L		0x239	/* .6. Data BAT Reg 4 Lower */
-#define	SPI_DBAT5U		0x23a	/* .6. Data BAT Reg 5 Upper */
-#define	SPI_DBAT5L		0x23b	/* .6. Data BAT Reg 5 Lower */
-#define	SPI_DBAT6U		0x23c	/* .6. Data BAT Reg 6 Upper */
-#define	SPI_DBAT6L		0x23d	/* .6. Data BAT Reg 6 Lower */
-#define	SPI_DBAT7U		0x23e	/* .6. Data BAT Reg 7 Upper */
-#define	SPI_DBAT7L		0x23f	/* .6. Data BAT Reg 7 Lower */
+#define	SPR_IBAT0U		0x210	/* .6. Instruction BAT Reg 0 Upper */
+#define	SPR_IBAT0L		0x211	/* .6. Instruction BAT Reg 0 Lower */
+#define	SPR_IBAT1U		0x212	/* .6. Instruction BAT Reg 1 Upper */
+#define	SPR_IBAT1L		0x213	/* .6. Instruction BAT Reg 1 Lower */
+#define	SPR_IBAT2U		0x214	/* .6. Instruction BAT Reg 2 Upper */
+#define	SPR_IBAT2L		0x215	/* .6. Instruction BAT Reg 2 Lower */
+#define	SPR_IBAT3U		0x216	/* .6. Instruction BAT Reg 3 Upper */
+#define	SPR_IBAT3L		0x217	/* .6. Instruction BAT Reg 3 Lower */
+#define	SPR_DBAT0U		0x218	/* .6. Data BAT Reg 0 Upper */
+#define	SPR_DBAT0L		0x219	/* .6. Data BAT Reg 0 Lower */
+#define	SPR_DBAT1U		0x21a	/* .6. Data BAT Reg 1 Upper */
+#define	SPR_DBAT1L		0x21b	/* .6. Data BAT Reg 1 Lower */
+#define	SPR_DBAT2U		0x21c	/* .6. Data BAT Reg 2 Upper */
+#define	SPR_DBAT2L		0x21d	/* .6. Data BAT Reg 2 Lower */
+#define	SPR_DBAT3U		0x21e	/* .6. Data BAT Reg 3 Upper */
+#define	SPR_DBAT3L		0x21f	/* .6. Data BAT Reg 3 Lower */
+#define SPR_IC_CST		0x230	/* ..8 Instruction Cache CSR */
+#define  IC_CST_IEN		0x80000000 /* I cache is ENabled   (RO) */
+#define  IC_CST_CMD_INVALL	0x0c000000 /* I cache invalidate all */
+#define  IC_CST_CMD_UNLOCKALL	0x0a000000 /* I cache unlock all */
+#define  IC_CST_CMD_UNLOCK	0x08000000 /* I cache unlock block */
+#define  IC_CST_CMD_LOADLOCK	0x06000000 /* I cache load & lock block */
+#define  IC_CST_CMD_DISABLE	0x04000000 /* I cache disable */
+#define  IC_CST_CMD_ENABLE	0x02000000 /* I cache enable */
+#define  IC_CST_CCER1		0x00200000 /* I cache error type 1 (RO) */
+#define  IC_CST_CCER2		0x00100000 /* I cache error type 2 (RO) */
+#define  IC_CST_CCER3		0x00080000 /* I cache error type 3 (RO) */
+#define	SPR_IBAT4U		0x230	/* .6. Instruction BAT Reg 4 Upper */
+#define SPR_IC_ADR		0x231	/* ..8 Instruction Cache Address */
+#define	SPR_IBAT4L		0x231	/* .6. Instruction BAT Reg 4 Lower */
+#define SPR_IC_DAT		0x232	/* ..8 Instruction Cache Data */
+#define	SPR_IBAT5U		0x232	/* .6. Instruction BAT Reg 5 Upper */
+#define	SPR_IBAT5L		0x233	/* .6. Instruction BAT Reg 5 Lower */
+#define	SPR_IBAT6U		0x234	/* .6. Instruction BAT Reg 6 Upper */
+#define	SPR_IBAT6L		0x235	/* .6. Instruction BAT Reg 6 Lower */
+#define	SPR_IBAT7U		0x236	/* .6. Instruction BAT Reg 7 Upper */
+#define	SPR_IBAT7L		0x237	/* .6. Instruction BAT Reg 7 Lower */
+#define SPR_DC_CST		0x230	/* ..8 Data Cache CSR */
+#define  DC_CST_DEN		0x80000000 /* D cache ENabled (RO) */
+#define  DC_CST_DFWT		0x40000000 /* D cache Force Write-Thru (RO) */
+#define  DC_CST_LES		0x20000000 /* D cache Little Endian Swap (RO) */
+#define  DC_CST_CMD_FLUSH	0x0e000000 /* D cache invalidate all */
+#define  DC_CST_CMD_INVALL	0x0c000000 /* D cache invalidate all */
+#define  DC_CST_CMD_UNLOCKALL	0x0a000000 /* D cache unlock all */
+#define  DC_CST_CMD_UNLOCK	0x08000000 /* D cache unlock block */
+#define  DC_CST_CMD_CLRLESWAP	0x07000000 /* D cache clr little-endian swap */
+#define  DC_CST_CMD_LOADLOCK	0x06000000 /* D cache load & lock block */
+#define  DC_CST_CMD_SETLESWAP	0x05000000 /* D cache set little-endian swap */
+#define  DC_CST_CMD_DISABLE	0x04000000 /* D cache disable */
+#define  DC_CST_CMD_CLRFWT	0x03000000 /* D cache clear forced write-thru */
+#define  DC_CST_CMD_ENABLE	0x02000000 /* D cache enable */
+#define  DC_CST_CMD_SETFWT	0x01000000 /* D cache set forced write-thru */
+#define  DC_CST_CCER1		0x00200000 /* D cache error type 1 (RO) */
+#define  DC_CST_CCER2		0x00100000 /* D cache error type 2 (RO) */
+#define  DC_CST_CCER3		0x00080000 /* D cache error type 3 (RO) */
+#define	SPR_DBAT4U		0x238	/* .6. Data BAT Reg 4 Upper */
+#define SPR_DC_ADR		0x231	/* ..8 Data Cache Address */
+#define	SPR_DBAT4L		0x239	/* .6. Data BAT Reg 4 Lower */
+#define SPR_DC_DAT		0x232	/* ..8 Data Cache Data */
+#define	SPR_DBAT5U		0x23a	/* .6. Data BAT Reg 5 Upper */
+#define	SPR_DBAT5L		0x23b	/* .6. Data BAT Reg 5 Lower */
+#define	SPR_DBAT6U		0x23c	/* .6. Data BAT Reg 6 Upper */
+#define	SPR_DBAT6L		0x23d	/* .6. Data BAT Reg 6 Lower */
+#define	SPR_DBAT7U		0x23e	/* .6. Data BAT Reg 7 Upper */
+#define	SPR_DBAT7L		0x23f	/* .6. Data BAT Reg 7 Lower */
+#define	SPR_MI_CTR		0x310	/* ..8 IMMU control */
+#define  Mx_CTR_GPM		0x80000000 /* Group Protection Mode */
+#define  Mx_CTR_PPM		0x40000000 /* Page Protection Mode */
+#define  Mx_CTR_CIDEF		0x20000000 /* Cache-Inhibit DEFault */
+#define  MD_CTR_WTDEF		0x20000000 /* Write-Through DEFault */
+#define  Mx_CTR_RSV4		0x08000000 /* Reserve 4 TLB entries */
+#define  MD_CTR_TWAM		0x04000000 /* TableWalk Assist Mode */
+#define  Mx_CTR_PPCS		0x02000000 /* Priv/user state compare mode */
+#define  Mx_CTR_TLB_INDX	0x000001f0 /* TLB index mask */
+#define  Mx_CTR_TLB_INDX_BITPOS	8	  /* TLB index shift */
+#define	SPR_MI_AP		0x312	/* ..8 IMMU access protection */
+#define  Mx_GP_SUPER(n)		(0 << (2*(15-(n)))) /* access is supervisor */
+#define  Mx_GP_PAGE		(1 << (2*(15-(n)))) /* access is page protect */
+#define  Mx_GP_SWAPPED		(2 << (2*(15-(n)))) /* access is swapped */
+#define  Mx_GP_USER		(3 << (2*(15-(n)))) /* access is user */
+#define	SPR_MI_EPN		0x313	/* ..8 IMMU effective number */
+#define  Mx_EPN_EPN		0xfffff000 /* Effective Page Number mask */
+#define  Mx_EPN_EV		0x00000020 /* Entry Valid */
+#define  Mx_EPN_ASID		0x0000000f /* Address Space ID */
+#define	SPR_MI_TWC		0x315	/* ..8 IMMU tablewalk control */
+#define  MD_TWC_L2TB		0xfffff000 /* Level-2 Tablewalk Base */
+#define  Mx_TWC_APG		0x000001e0 /* Access Protection Group */
+#define  Mx_TWC_G		0x00000010 /* Guarded memory */
+#define  Mx_TWC_PS		0x0000000c /* Page Size (L1) */
+#define  MD_TWC_WT		0x00000002 /* Write-Through */
+#define  Mx_TWC_V		0x00000001 /* Entry Valid */
+#define	SPR_MI_RPN		0x316	/* ..8 IMMU real (phys) page number */
+#define  Mx_RPN_RPN		0xfffff000 /* Real Page Number */
+#define  Mx_RPN_PP		0x00000ff0 /* Page Protection */
+#define  Mx_RPN_SPS		0x00000008 /* Small Page Size */
+#define  Mx_RPN_SH		0x00000004 /* SHared page */
+#define  Mx_RPN_CI		0x00000002 /* Cache Inhibit */
+#define  Mx_RPN_V		0x00000001 /* Valid */
+#define	SPR_MD_CTR		0x318	/* ..8 DMMU control */
+#define	SPR_M_CASID		0x319	/* ..8 CASID */
+#define  M_CASID		0x0000000f /* Current AS Id */
+#define	SPR_MD_AP		0x31a	/* ..8 DMMU access protection */
+#define	SPR_MD_EPN		0x31b	/* ..8 DMMU effective number */
+#define	SPR_M_TWB		0x31c	/* ..8 MMU tablewalk base */
+#define  M_TWB_L1TB		0xfffff000 /* level-1 translation base */
+#define  M_TWB_L1INDX		0x00000ffc /* level-1 index */
+#define	SPR_MD_TWC		0x31d	/* ..8 DMMU tablewalk control */
+#define	SPR_MD_RPN		0x31e	/* ..8 DMMU real (phys) page number */
+#define	SPR_MD_TW		0x31f	/* ..8 MMU tablewalk scratch */
+#define	SPR_MI_CAM		0x330	/* ..8 IMMU CAM entry read */
+#define	SPR_MI_RAM0		0x331	/* ..8 IMMU RAM entry read reg 0 */
+#define	SPR_MI_RAM1		0x332	/* ..8 IMMU RAM entry read reg 1 */
+#define	SPR_MD_CAM		0x338	/* ..8 IMMU CAM entry read */
+#define	SPR_MD_RAM0		0x339	/* ..8 IMMU RAM entry read reg 0 */
+#define	SPR_MD_RAM1		0x33a	/* ..8 IMMU RAM entry read reg 1 */
 #define	SPR_UMMCR2		0x3a0	/* .6. User Monitor Mode Control Register 2 */
 #define	SPR_UMMCR0		0x3a8	/* .6. User Monitor Mode Control Register 0 */
 #define	SPR_USIA		0x3ab	/* .6. User Sampled Instruction Address */
@@ -288,45 +390,60 @@
 #define	SPR_IAC2		0x3f5	/* 4.. Instruction Address Compare 2 */
 #define	SPR_DABR		0x3f5	/* .6. Data Address Breakpoint Register */
 #define	SPR_DAC1		0x3f6	/* 4.. Data Address Compare 1 */
+#define	SPR_MSSCR0		0x3f6	/* .6. Memory SubSystem Control Register */
+#define	  MSSCR0_SHDEN		  0x80000000 /* 0: Shared-state enable */
+#define	  MSSCR0_SHDPEN3	  0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */
+#define	  MSSCR0_L1INTVEN	  0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */
+#define	  MSSCR0_L2INTVEN	  0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/
+#define	  MSSCR0_DL1HWF		  0x00800000 /* 8: L1 data cache hardware flush */
+#define	  MSSCR0_MBO		  0x00400000 /* 9: must be one */
+#define	  MSSCR0_EMODE		  0x00200000 /* 10: MPX bus mode (read-only) */
+#define	  MSSCR0_ABD		  0x00100000 /* 11: address bus driven (read-only) */
+#define	  MSSCR0_MBZ		  0x000fffff /* 12-31: must be zero */
 #define	SPR_DAC2		0x3f7	/* 4.. Data Address Compare 2 */
 #define	SPR_L2PM		0x3f8	/* .6. L2 Private Memory Control Register */
 #define	SPR_L2CR		0x3f9	/* .6. L2 Control Register */
-#define   L2CR_L2E		  0x80000000 /* 0: L2 enable */
-#define   L2CR_L2PE		  0x40000000 /* 1: L2 data parity enable */
-#define   L2CR_L2SIZ		  0x30000000 /* 2-3: L2 size */
-#define    L2SIZ_2M		  0x00000000
-#define    L2SIZ_256K		  0x10000000
-#define    L2SIZ_512K		  0x20000000
-#define    L2SIZ_1M		  0x30000000
-#define   L2CR_L2CLK		  0x0e000000 /* 4-6: L2 clock ratio */
-#define    L2CLK_DIS		  0x00000000 /* disable L2 clock */
-#define    L2CLK_10		  0x02000000 /* core clock / 1   */
-#define    L2CLK_15		  0x04000000 /*            / 1.5 */
-#define    L2CLK_20		  0x08000000 /*            / 2   */
-#define    L2CLK_25		  0x0a000000 /*            / 2.5 */
-#define    L2CLK_30		  0x0c000000 /*            / 3   */
-#define   L2CR_L2RAM		  0x01800000 /* 7-8: L2 RAM type */
-#define    L2RAM_FLOWTHRU_BURST	  0x00000000
-#define    L2RAM_PIPELINE_BURST	  0x01000000
-#define    L2RAM_PIPELINE_LATE	  0x01800000
-#define   L2CR_L2DO		  0x00400000 /* 9: L2 data-only.
+#define	  L2CR_L2E		  0x80000000 /* 0: L2 enable */
+#define	  L2CR_L2PE		  0x40000000 /* 1: L2 data parity enable */
+#define	  L2CR_L2SIZ		  0x30000000 /* 2-3: L2 size */
+#define	   L2SIZ_2M		  0x00000000
+#define	   L2SIZ_256K		  0x10000000
+#define	   L2SIZ_512K		  0x20000000
+#define	   L2SIZ_1M		  0x30000000
+#define	  L2CR_L2CLK		  0x0e000000 /* 4-6: L2 clock ratio */
+#define	   L2CLK_DIS		  0x00000000 /* disable L2 clock */
+#define	   L2CLK_10		  0x02000000 /* core clock / 1   */
+#define	   L2CLK_15		  0x04000000 /*            / 1.5 */
+#define	   L2CLK_20		  0x08000000 /*            / 2   */
+#define	   L2CLK_25		  0x0a000000 /*            / 2.5 */
+#define	   L2CLK_30		  0x0c000000 /*            / 3   */
+#define	  L2CR_L2RAM		  0x01800000 /* 7-8: L2 RAM type */
+#define	   L2RAM_FLOWTHRU_BURST	  0x00000000
+#define	   L2RAM_PIPELINE_BURST	  0x01000000
+#define	   L2RAM_PIPELINE_LATE	  0x01800000
+#define	  L2CR_L2DO		  0x00400000 /* 9: L2 data-only.
 				      Setting this bit disables instruction
 				      caching. */
-#define   L2CR_L2I		  0x00200000 /* 10: L2 global invalidate. */
-#define   L2CR_L2CTL		  0x00100000 /* 11: L2 RAM control (ZZ enable).
+#define	  L2CR_L2I		  0x00200000 /* 10: L2 global invalidate. */
+#define	  L2CR_L2CTL		  0x00100000 /* 11: L2 RAM control (ZZ enable).
 				      Enables automatic operation of the
 				      L2ZZ (low-power mode) signal. */
-#define   L2CR_L2WT		  0x00080000 /* 12: L2 write-through. */
-#define   L2CR_L2TS		  0x00040000 /* 13: L2 test support. */
-#define   L2CR_L2OH		  0x00030000 /* 14-15: L2 output hold. */
-#define   L2CR_L2SL		  0x00008000 /* 16: L2 DLL slow. */
-#define   L2CR_L2DF		  0x00004000 /* 17: L2 differential clock. */
-#define   L2CR_L2BYP		  0x00002000 /* 18: L2 DLL bypass. */
-#define   L2CR_L2IP		  0x00000001 /* 31: L2 global invalidate in */
+#define	  L2CR_L2WT		  0x00080000 /* 12: L2 write-through. */
+#define	  L2CR_L2TS		  0x00040000 /* 13: L2 test support. */
+#define	  L2CR_L2OH		  0x00030000 /* 14-15: L2 output hold. */
+#define	  L2CR_L2SL		  0x00008000 /* 16: L2 DLL slow. */
+#define	  L2CR_L2DF		  0x00004000 /* 17: L2 differential clock. */
+#define	  L2CR_L2BYP		  0x00002000 /* 18: L2 DLL bypass. */
+#define	  L2CR_L2FA		  0x00001000 /* 19: L2 flush assist (for software flush). */
+#define	  L2CR_L2HWF		  0x00000800 /* 20: L2 hardware flush. */
+#define	  L2CR_L2IO		  0x00000400 /* 21: L2 instruction-only. */
+#define	  L2CR_L2CLKSTP		  0x00000200 /* 22: L2 clock stop. */
+#define	  L2CR_L2DRO		  0x00000100 /* 23: L2DLL rollover checkstop enable. */
+#define	  L2CR_L2IP		  0x00000001 /* 31: L2 global invalidate in */
 					     /*     progress (read only). */
 #define	SPR_L3CR		0x3fa	/* .6. L3 Control Register */
-#define   L3CR_L3E		  0x80000000 /*  0: L3 enable */
-#define   L3CR_L3SIZ		  0x10000000 /*  3: L3 size (0=1MB, 1=2MB) */
+#define	  L3CR_L3E		  0x80000000 /*  0: L3 enable */
+#define	  L3CR_L3SIZ		  0x10000000 /*  3: L3 size (0=1MB, 1=2MB) */
 #define	SPR_DCCR		0x3fa	/* 4.. Data Cache Cachability Register */
 #define	SPR_ICCR		0x3fb	/* 4.. Instruction Cache Cachability Register */
 #define	SPR_THRM1		0x3fc	/* .6. Thermal Management Register */