Rename cpu_config_l2cr() to cpu_print_cacheinfo(). We're not

configuring the L2 cache on the BSP. Nor the L3 cache. We
merely print the settings.

Save the L2 and L3 cache configuration in global values so
that we know how to configure the cache on APs.

1 files changed, 47 insertions, 103 deletions

diff --git a/sys/powerpc/powerpc/cpu.c b/sys/powerpc/powerpc/cpu.c
index 93cb655..e2a4f71 100644
--- a/sys/powerpc/powerpc/cpu.c
+++ b/sys/powerpc/powerpc/cpu.c
@@ -107,10 +107,11 @@ static const struct cputab models[] = {
 static char model[64];
 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
 
-static register_t	l2cr_config = 0;
+register_t	l2cr_config = 0;
+register_t	l3cr_config = 0;
 
 static void	cpu_print_speed(void);
-static void	cpu_config_l2cr(u_int, uint16_t);
+static void	cpu_print_cacheinfo(u_int, uint16_t);
 
 void
 cpu_setup(u_int cpuid)
@@ -261,7 +262,12 @@ cpu_setup(u_int cpuid)
 		case MPC7457:
 			cpu_print_speed();
 			printf("\n");
-			cpu_config_l2cr(cpuid, vers);
+
+			l2cr_config = mfspr(SPR_L2CR);
+			l3cr_config = mfspr(SPR_L3CR);
+
+			if (bootverbose)
+				cpu_print_cacheinfo(cpuid, vers);
 			break;
 		default:
 			printf("\n");
@@ -285,114 +291,52 @@ cpu_print_speed(void)
 }
 
 void
-cpu_config_l2cr(u_int cpuid, uint16_t vers)
+cpu_print_cacheinfo(u_int cpuid, uint16_t vers)
 {
-	u_int l2cr, x, msr;
+	uint32_t hid;
 
-	l2cr = mfspr(SPR_L2CR);
 
-	/*
-	 * For MP systems, the firmware may only configure the L2 cache
-	 * on the first CPU.  In this case, assume that the other CPUs
-	 * should use the same value for L2CR.
-	 */
-	if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) {
-		l2cr_config = l2cr;
-	}
+	hid = mfspr(SPR_HID0);
+	printf("cpu%u: ", cpuid);
+	printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
+	printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
 
-	/*
-	 * Configure L2 cache if not enabled.
-	 */
-	if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) {
-		l2cr = l2cr_config;
-
-		/* Disable interrupts and set the cache config bits. */
-		msr = mfmsr();
-		mtmsr(msr & ~PSL_EE);
-#ifdef ALTIVEC
-		if (cpu_altivec)
-			__asm __volatile("dssall");
-#endif
-		__asm __volatile("sync");
-		mtspr(SPR_L2CR, l2cr & ~L2CR_L2E);
-		__asm __volatile("sync");
-
-		/* Wait for L2 clock to be stable (640 L2 clocks). */
-		DELAY(100);
-
-		/* Invalidate all L2 contents. */
-		mtspr(SPR_L2CR, l2cr | L2CR_L2I);
-		do {
-			x = mfspr(SPR_L2CR);
-		} while (x & L2CR_L2IP);
-
-		/* Enable L2 cache. */
-		l2cr |= L2CR_L2E;
-		mtspr(SPR_L2CR, l2cr);
-		mtmsr(msr);
-	}
-
-	if (!bootverbose)
-		return;
-
-	printf("cpu%d: ", cpuid);
-
-	if (l2cr & L2CR_L2E) {
-		if (vers == MPC7450 ||
-		    vers == MPC7455 ||
-		    vers == MPC7457) {
-			u_int l3cr;
-
-			printf("256KB L2 cache");
-
-			l3cr = mfspr(SPR_L3CR);
-			if (l3cr & L3CR_L3E)
-				printf(", %cMB L3 backside cache",
-				   l3cr & L3CR_L3SIZ ? '2' : '1');
+	printf("cpu%u: ", cpuid);
+  	if (l2cr_config & L2CR_L2E) {
+		switch (vers) {
+		case MPC7450:
+		case MPC7455:
+		case MPC7457:
+			printf("256KB L2 cache, ");
+			if (l3cr_config & L3CR_L3E)
+				printf("%cMB L3 backside cache",
+				    l3cr_config & L3CR_L3SIZ ? '2' : '1');
+			else
+				printf("L3 cache disabled");
 			printf("\n");
-			return;
-		}
-		if (vers == IBM750FX) {
-			printf("512KB L2 cache\n");
-			return;
-		}
-		switch (l2cr & L2CR_L2SIZ) {
-		case L2SIZ_256K:
-			printf("256KB");
-			break;
-		case L2SIZ_512K:
-			printf("512KB");
-			break;
-		case L2SIZ_1M:
-			printf("1MB");
 			break;
+		case IBM750FX:
+			printf("512KB L2 cache\n");
+			break; 
 		default:
-			printf("unknown size");
-		}
-		if (l2cr & L2CR_L2WT) {
-			printf(" write-through");
-		} else {
-			printf(" write-back");
-		}
-		switch (l2cr & L2CR_L2RAM) {
-		case L2RAM_FLOWTHRU_BURST:
-			printf(" flow-through synchronous burst SRAM");
-			break;
-		case L2RAM_PIPELINE_BURST:
-			printf(" pipelined synchronous burst SRAM");
-			break;
-		case L2RAM_PIPELINE_LATE:
-			printf(" pipelined synchronous late-write SRAM");
+			switch (l2cr_config & L2CR_L2SIZ) {
+			case L2SIZ_256K:
+				printf("256KB ");
+				break;
+			case L2SIZ_512K:
+				printf("512KB ");
+				break;
+			case L2SIZ_1M:
+				printf("1MB ");
+				break;
+			}
+			printf("write-%s", (l2cr_config & L2CR_L2WT)
+			    ? "through" : "back");
+			if (l2cr_config & L2CR_L2PE)
+				printf(", with parity");
+			printf(" backside cache\n");
 			break;
-		default:
-			printf(" unknown type");
 		}
-
-		if (l2cr & L2CR_L2PE)
-			printf(" with parity");
-		printf(" backside cache");
 	} else
-		printf("L2 cache not enabled");
-
-	printf("\n");
+		printf("L2 cache disabled\n");
 }