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author | ian <ian@FreeBSD.org> | 2015-02-23 20:09:05 +0000 |
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committer | ian <ian@FreeBSD.org> | 2015-02-23 20:09:05 +0000 |
commit | d8abe6df98c0decd3b7509d6e722e968df5020da (patch) | |
tree | 33e2044573e7bcc1fe63d3170f2ce2f9256d668d /sys/powerpc/pseries | |
parent | 45a2a34766ae485750a4e5a76cb0b0d57d32748e (diff) | |
download | FreeBSD-src-d8abe6df98c0decd3b7509d6e722e968df5020da.zip FreeBSD-src-d8abe6df98c0decd3b7509d6e722e968df5020da.tar.gz |
There is no reason to do i+dcache writeback and invalidate when changing
the translation table (this may be left over from armv5 days). It's
especially bad to do so using a cache operation that isn't coherent on
SMP systems.
Submitted by: Michal Meloun
Diffstat (limited to 'sys/powerpc/pseries')
0 files changed, 0 insertions, 0 deletions