MFC r261309

Unbreak non-SMP builds.  This was broken by r259284.  Also, reorganize the
code introduced in that revision a bit.

2 files changed, 14 insertions, 177 deletions

diff --git a/sys/powerpc/powermac/platform_powermac.c b/sys/powerpc/powermac/platform_powermac.c
index 82420dc..ce73622 100644
--- a/sys/powerpc/powermac/platform_powermac.c
+++ b/sys/powerpc/powermac/platform_powermac.c
@@ -38,11 +38,14 @@ __FBSDID("$FreeBSD$");
 #include <vm/vm.h>
 #include <vm/pmap.h>
 
+#include <machine/altivec.h>	/* For save_vec() */
 #include <machine/bus.h>
 #include <machine/cpu.h>
+#include <machine/fpu.h>	/* For save_fpu() */
 #include <machine/hid.h>
 #include <machine/platformvar.h>
 #include <machine/pmap.h>
+#include <machine/setjmp.h>
 #include <machine/smp.h>
 #include <machine/spr.h>
 
@@ -51,9 +54,7 @@ __FBSDID("$FreeBSD$");
 
 #include "platform_if.h"
 
-#ifdef SMP
 extern void *ap_pcpu;
-#endif
 
 static int powermac_probe(platform_t);
 static int powermac_attach(platform_t);
@@ -65,6 +66,7 @@ static int powermac_smp_next_cpu(platform_t, struct cpuref *cpuref);
 static int powermac_smp_get_bsp(platform_t, struct cpuref *cpuref);
 static int powermac_smp_start_cpu(platform_t, struct pcpu *cpu);
 static void powermac_reset(platform_t);
+static void powermac_sleep(platform_t);
 
 static platform_method_t powermac_methods[] = {
 	PLATFORMMETHOD(platform_probe, 		powermac_probe),
@@ -78,6 +80,7 @@ static platform_method_t powermac_methods[] = {
 	PLATFORMMETHOD(platform_smp_start_cpu,	powermac_smp_start_cpu),
 
 	PLATFORMMETHOD(platform_reset,		powermac_reset),
+	PLATFORMMETHOD(platform_sleep,		powermac_sleep),
 
 	PLATFORMMETHOD_END
 };
@@ -326,113 +329,17 @@ powermac_smp_start_cpu(platform_t plat, struct pcpu *pc)
 #endif
 }
 
-/* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */
-void
-flush_disable_caches(void)
-{
-	register_t msr;
-	register_t msscr0;
-	register_t cache_reg;
-	volatile uint32_t *memp;
-	uint32_t temp;
-	int i;
-	int x;
-
-	msr = mfmsr();
-	powerpc_sync();
-	mtmsr(msr & ~(PSL_EE | PSL_DR));
-	msscr0 = mfspr(SPR_MSSCR0);
-	msscr0 &= ~MSSCR0_L2PFE;
-	mtspr(SPR_MSSCR0, msscr0);
-	powerpc_sync();
-	isync();
-	__asm__ __volatile__("dssall; sync");
-	powerpc_sync();
-	isync();
-	__asm__ __volatile__("dcbf 0,%0" :: "r"(0));
-	__asm__ __volatile__("dcbf 0,%0" :: "r"(0));
-	__asm__ __volatile__("dcbf 0,%0" :: "r"(0));
-
-	/* Lock the L1 Data cache. */
-	mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF);
-	powerpc_sync();
-	isync();
-
-	mtspr(SPR_LDSTCR, 0);
-
-	/*
-	 * Perform this in two stages: Flush the cache starting in RAM, then do it
-	 * from ROM.
-	 */
-	memp = (volatile uint32_t *)0x00000000;
-	for (i = 0; i < 128 * 1024; i++) {
-		temp = *memp;
-		__asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
-		memp += 32/sizeof(*memp);
-	}
-
-	memp = (volatile uint32_t *)0xfff00000;
-	x = 0xfe;
-
-	for (; x != 0xff;) {
-		mtspr(SPR_LDSTCR, x);
-		for (i = 0; i < 128; i++) {
-			temp = *memp;
-			__asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
-			memp += 32/sizeof(*memp);
-		}
-		x = ((x << 1) | 1) & 0xff;
-	}
-	mtspr(SPR_LDSTCR, 0);
-
-	cache_reg = mfspr(SPR_L2CR);
-	if (cache_reg & L2CR_L2E) {
-		cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450);
-		mtspr(SPR_L2CR, cache_reg);
-		powerpc_sync();
-		mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF);
-		while (mfspr(SPR_L2CR) & L2CR_L2HWF)
-			; /* Busy wait for cache to flush */
-		powerpc_sync();
-		cache_reg &= ~L2CR_L2E;
-		mtspr(SPR_L2CR, cache_reg);
-		powerpc_sync();
-		mtspr(SPR_L2CR, cache_reg | L2CR_L2I);
-		powerpc_sync();
-		while (mfspr(SPR_L2CR) & L2CR_L2I)
-			; /* Busy wait for L2 cache invalidate */
-		powerpc_sync();
-	}
-
-	cache_reg = mfspr(SPR_L3CR);
-	if (cache_reg & L3CR_L3E) {
-		cache_reg &= ~(L3CR_L3IO | L3CR_L3DO);
-		mtspr(SPR_L3CR, cache_reg);
-		powerpc_sync();
-		mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF);
-		while (mfspr(SPR_L3CR) & L3CR_L3HWF)
-			; /* Busy wait for cache to flush */
-		powerpc_sync();
-		cache_reg &= ~L3CR_L3E;
-		mtspr(SPR_L3CR, cache_reg);
-		powerpc_sync();
-		mtspr(SPR_L3CR, cache_reg | L3CR_L3I);
-		powerpc_sync();
-		while (mfspr(SPR_L3CR) & L3CR_L3I)
-			; /* Busy wait for L3 cache invalidate */
-		powerpc_sync();
-	}
-
-	mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE);
-	powerpc_sync();
-	isync();
-
-	mtmsr(msr);
-}
-
 static void
 powermac_reset(platform_t platform)
 {
 	OF_reboot();
 }
 
+void
+powermac_sleep(platform_t platform)
+{
+
+	*(unsigned long *)0x80 = 0x100;
+	cpu_sleep();
+}
+
diff --git a/sys/powerpc/powermac/pmu.c b/sys/powerpc/powermac/pmu.c
index c6bd1b0..913845e 100644
--- a/sys/powerpc/powermac/pmu.c
+++ b/sys/powerpc/powermac/pmu.c
@@ -45,17 +45,14 @@ __FBSDID("$FreeBSD$");
 #include <dev/led/led.h>
 
 #include <machine/_inttypes.h>
-#include <machine/altivec.h>	/* For save_vec() */
 #include <machine/bus.h>
 #include <machine/cpu.h>
-#include <machine/fpu.h>	/* For save_fpu() */
 #include <machine/hid.h>
 #include <machine/intr_machdep.h>
 #include <machine/md_var.h>
 #include <machine/pcb.h>
 #include <machine/pio.h>
 #include <machine/resource.h>
-#include <machine/setjmp.h>
 
 #include <vm/vm.h>
 #include <vm/pmap.h>
@@ -106,7 +103,6 @@ static int	pmu_acline_state(SYSCTL_HANDLER_ARGS);
 static int	pmu_query_battery(struct pmu_softc *sc, int batt, 
 		    struct pmu_battstate *info);
 static int	pmu_battquery_sysctl(SYSCTL_HANDLER_ARGS);
-static void	pmu_sleep_int(void);
 
 /*
  * List of battery-related sysctls we might ask for
@@ -1031,72 +1027,6 @@ pmu_settime(device_t dev, struct timespec *ts)
 	return (0);
 }
 
-static register_t sprgs[4];
-static register_t srrs[2];
-extern void *ap_pcpu;
-
-void pmu_sleep_int(void)
-{
-	static u_quad_t timebase = 0;
-	jmp_buf resetjb;
-	struct thread *fputd;
-	struct thread *vectd;
-	register_t hid0;
-	register_t msr;
-	register_t saved_msr;
-
-	ap_pcpu = pcpup;
-
-	PCPU_SET(restore, &resetjb);
-
-	*(unsigned long *)0x80 = 0x100;
-	saved_msr = mfmsr();
-	fputd = PCPU_GET(fputhread);
-	vectd = PCPU_GET(vecthread);
-	if (fputd != NULL)
-		save_fpu(fputd);
-	if (vectd != NULL)
-		save_vec(vectd);
-	if (setjmp(resetjb) == 0) {
-		sprgs[0] = mfspr(SPR_SPRG0);
-		sprgs[1] = mfspr(SPR_SPRG1);
-		sprgs[2] = mfspr(SPR_SPRG2);
-		sprgs[3] = mfspr(SPR_SPRG3);
-		srrs[0] = mfspr(SPR_SRR0);
-		srrs[1] = mfspr(SPR_SRR1);
-		timebase = mftb();
-		powerpc_sync();
-		flush_disable_caches();
-		hid0 = mfspr(SPR_HID0);
-		hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP;
-		powerpc_sync();
-		isync();
-		msr = mfmsr() | PSL_POW;
-		mtspr(SPR_HID0, hid0);
-		powerpc_sync();
-
-		while (1)
-			mtmsr(msr);
-	}
-	mttb(timebase);
-	PCPU_SET(curthread, curthread);
-	PCPU_SET(curpcb, curthread->td_pcb);
-	pmap_activate(curthread);
-	powerpc_sync();
-	mtspr(SPR_SPRG0, sprgs[0]);
-	mtspr(SPR_SPRG1, sprgs[1]);
-	mtspr(SPR_SPRG2, sprgs[2]);
-	mtspr(SPR_SPRG3, sprgs[3]);
-	mtspr(SPR_SRR0, srrs[0]);
-	mtspr(SPR_SRR1, srrs[1]);
-	mtmsr(saved_msr);
-	if (fputd == curthread)
-		enable_fpu(curthread);
-	if (vectd == curthread)
-		enable_vec(curthread);
-	powerpc_sync();
-}
-
 int
 pmu_set_speed(int low_speed)
 {
@@ -1114,7 +1044,7 @@ pmu_set_speed(int low_speed)
 	sleepcmd[4] = low_speed;
 	pmu_send(sc, PMU_CPU_SPEED, 5, sleepcmd, 16, resp);
 	unin_chip_sleep(NULL, 1);
-	pmu_sleep_int();
+	platform_sleep();
 	unin_chip_wake(NULL);
 
 	mtdec(1);	/* Force a decrementer exception */