diff options
| author | jhibbits <jhibbits@FreeBSD.org> | 2014-03-14 00:12:53 +0000 |
|---|---|---|
| committer | jhibbits <jhibbits@FreeBSD.org> | 2014-03-14 00:12:53 +0000 |
| commit | 74bf659c83cf1882928c8cdc518889ea7dee45a5 (patch) | |
| tree | 16f2f6c6bbc74af38d48134a3be33d23902ee61c /sys/powerpc/include | |
| parent | a2a8cc80bfd0d213851bd6c0d45e03b0386dcde2 (diff) | |
| download | FreeBSD-src-74bf659c83cf1882928c8cdc518889ea7dee45a5.zip FreeBSD-src-74bf659c83cf1882928c8cdc518889ea7dee45a5.tar.gz | |
MFC r261342
Add hwpmc(4) support for the PowerPC 970 class processors, direct events.
This also fixes asserts on removal of the module for the mpc74xx.
The PowerPC 970 processors have two different types of events: direct events
and indirect events. Thus far only direct events are supported. I included
some documentation in the driver on how indirect events work, but support is
for the future.
Diffstat (limited to 'sys/powerpc/include')
| -rw-r--r-- | sys/powerpc/include/pmc_mdep.h | 1 | ||||
| -rw-r--r-- | sys/powerpc/include/spr.h | 36 |
2 files changed, 22 insertions, 15 deletions
diff --git a/sys/powerpc/include/pmc_mdep.h b/sys/powerpc/include/pmc_mdep.h index a0f2062..87dc76c 100644 --- a/sys/powerpc/include/pmc_mdep.h +++ b/sys/powerpc/include/pmc_mdep.h @@ -7,6 +7,7 @@ #ifndef _MACHINE_PMC_MDEP_H_ #define _MACHINE_PMC_MDEP_H_ +#define PMC_MDEP_CLASS_INDEX_CPU 1 #define PMC_MDEP_CLASS_INDEX_PPC7450 1 #define PMC_MDEP_CLASS_INDEX_PPC970 1 diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h index f275069..b9fb3c1 100644 --- a/sys/powerpc/include/spr.h +++ b/sys/powerpc/include/spr.h @@ -294,6 +294,27 @@ #define M_CASID 0x0000000f /* Current AS Id */ #define SPR_MD_AP 0x31a /* ..8 DMMU access protection */ #define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */ + +#define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */ +#define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ +#define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ +#define SPR_970MMCR1 0x31e /* ... Monitor Mode Control Register 1 (PPC 970) */ +#define SPR_970MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ +#define SPR_970MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ +#define SPR_970MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ +#define SPR_970MMCR1_PMC6SEL(x) (((x) & 0x1f) << 12) /* PMC 6 selector */ +#define SPR_970MMCR1_PMC7SEL(x) (((x) & 0x1f) << 7) /* PMC 7 selector */ +#define SPR_970MMCR1_PMC8SEL(x) (((x) & 0x1f) << 2) /* PMC 8 selector */ +#define SPR_970MMCRA 0x312 /* ... Monitor Mode Control Register 2 (PPC 970) */ +#define SPR_970PMC1 0x313 /* ... PMC 1 */ +#define SPR_970PMC2 0x314 /* ... PMC 2 */ +#define SPR_970PMC3 0x315 /* ... PMC 3 */ +#define SPR_970PMC4 0x316 /* ... PMC 4 */ +#define SPR_970PMC5 0x317 /* ... PMC 5 */ +#define SPR_970PMC6 0x318 /* ... PMC 6 */ +#define SPR_970PMC7 0x319 /* ... PMC 7 */ +#define SPR_970PMC8 0x31a /* ... PMC 8 */ + #define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */ #define M_TWB_L1TB 0xfffff000 /* level-1 translation base */ #define M_TWB_L1INDX 0x00000ffc /* level-1 index */ @@ -323,19 +344,6 @@ #define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */ #define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */ #define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */ - -#define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */ -#define SPR_970MMCR1 0x31e /* ... Monitor Mode Control Register 1 (PPC 970) */ -#define SPR_970MMCRA 0x312 /* ... Monitor Mode Control Register 2 (PPC 970) */ -#define SPR_970PMC1 0x313 /* ... PMC 1 */ -#define SPR_970PMC2 0x314 /* ... PMC 2 */ -#define SPR_970PMC3 0x315 /* ... PMC 3 */ -#define SPR_970PMC4 0x316 /* ... PMC 4 */ -#define SPR_970PMC5 0x317 /* ... PMC 5 */ -#define SPR_970PMC6 0x318 /* ... PMC 6 */ -#define SPR_970PMC7 0x319 /* ... PMC 7 */ -#define SPR_970PMC8 0x31a /* ... PMC 8 */ - #define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ #define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ #define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ @@ -354,8 +362,6 @@ #define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ #define SPR_MMCR0_PMC1SEL(x) (((x) & 0x3f) << 6) /* PMC1 selector */ #define SPR_MMCR0_PMC2SEL(x) (((x) & 0x3f) << 0) /* PMC2 selector */ -#define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ -#define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ #define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ #define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ #define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ |
