Let us manage differences of Book-E PowerPC variations i.e. vendor /

implementation specific vs. the common architecture definition.

Bring PPC4XX defines (PSL, SPR, TLB). Note the new definitions under
BOOKE_PPC4XX are not used in the code yet.

This change set is not supposed to affect existing E500 support, it's just
another reorg step before bringing support for E500mc, E5500 and PPC465.

Obtained from:	AppliedMicro, Freescale, Semihalf

8 files changed, 138 insertions, 29 deletions

diff --git a/sys/powerpc/include/pcpu.h b/sys/powerpc/include/pcpu.h
index 62094f8..bd14661 100644
--- a/sys/powerpc/include/pcpu.h
+++ b/sys/powerpc/include/pcpu.h
@@ -115,7 +115,7 @@ struct pmap;
 	PCPU_MD_COMMON_FIELDS	\
 	PCPU_MD_AIM_FIELDS
 #endif
-#ifdef E500
+#if defined(BOOKE)
 #define	PCPU_MD_FIELDS		\
 	PCPU_MD_COMMON_FIELDS	\
 	PCPU_MD_BOOKE_FIELDS
diff --git a/sys/powerpc/include/profile.h b/sys/powerpc/include/profile.h
index cde97ed..eb11fc9 100644
--- a/sys/powerpc/include/profile.h
+++ b/sys/powerpc/include/profile.h
@@ -172,12 +172,13 @@ __asm(	"	.globl	_mcount			\n" \
 #define	__PROFILE_VECTOR_BASE	EXC_RST
 #define	__PROFILE_VECTOR_TOP	(EXC_LAST + 0x100)
 #endif	/* AIM */
-#ifdef E500
+#if defined(BOOKE)
 extern char interrupt_vector_base[];
 extern char interrupt_vector_top[];
 #define	__PROFILE_VECTOR_BASE	(uintfptr_t)interrupt_vector_base
 #define	__PROFILE_VECTOR_TOP	(uintfptr_t)interrupt_vector_top
-#endif	/* E500 */
+#endif	/* BOOKE_E500 || BOOKE_PPC4XX */
+
 #endif	/* !COMPILING_LINT */
 
 #ifndef __PROFILE_VECTOR_BASE
diff --git a/sys/powerpc/include/psl.h b/sys/powerpc/include/psl.h
index 92bfa6c..b519266 100644
--- a/sys/powerpc/include/psl.h
+++ b/sys/powerpc/include/psl.h
@@ -35,7 +35,7 @@
 #ifndef	_MACHINE_PSL_H_
 #define	_MACHINE_PSL_H_
 
-#if defined(E500)
+#if defined(BOOKE_E500)
 /*
  * Machine State Register (MSR) - e500 core
  *
@@ -67,7 +67,29 @@
 #define PSL_KERNSET		(PSL_CE | PSL_ME | PSL_EE)
 #define PSL_USERSET		(PSL_KERNSET | PSL_PR)
 
-#else	/* if defined(E500) */
+#elif defined(BOOKE_PPC4XX)
+/*
+ * Machine State Register (MSR) - PPC4xx core
+ */
+#define PSL_WE		(0x80000000 >> 13) /* Wait State Enable */
+#define PSL_CE		(0x80000000 >> 14) /* Critical Interrupt Enable */
+#define PSL_EE		(0x80000000 >> 16) /* External Interrupt Enable */
+#define PSL_PR		(0x80000000 >> 17) /* Problem State */
+#define PSL_FP		(0x80000000 >> 18) /* Floating Point Available */
+#define PSL_ME		(0x80000000 >> 19) /* Machine Check Enable */
+#define PSL_FE0		(0x80000000 >> 20) /* Floating-point exception mode 0 */
+#define PSL_DWE		(0x80000000 >> 21) /* Debug Wait Enable */
+#define PSL_DE		(0x80000000 >> 22) /* Debug interrupt Enable */
+#define PSL_FE1		(0x80000000 >> 23) /* Floating-point exception mode 1 */
+#define PSL_IS		(0x80000000 >> 26) /* Instruction Address Space */
+#define PSL_DS		(0x80000000 >> 27) /* Data Address Space */
+
+#define PSL_KERNSET	(PSL_CE | PSL_ME | PSL_EE | PSL_FP)
+#define PSL_USERSET	(PSL_KERNSET | PSL_PR)
+
+#define PSL_FE_DFLT	0x00000000UL	/* default == none */
+
+#else	/* if defined(BOOKE_*) */
 /*
  * Machine State Register (MSR)
  *
@@ -127,5 +149,5 @@
 
 #define	PSL_USERSTATIC	(PSL_USERSET | PSL_IP | 0x87c0008c)
 
-#endif	/* if defined(E500) */
+#endif	/* if defined(BOOKE_E500) */
 #endif	/* _MACHINE_PSL_H_ */
diff --git a/sys/powerpc/include/pte.h b/sys/powerpc/include/pte.h
index 67cd5fd..b5d2ecf 100644
--- a/sys/powerpc/include/pte.h
+++ b/sys/powerpc/include/pte.h
@@ -163,7 +163,7 @@ extern u_int dsisr(void);
 #endif	/* _KERNEL */
 #endif	/* LOCORE */
 
-#else
+#else /* BOOKE */
 
 #include <machine/tlb.h>
 
@@ -224,6 +224,8 @@ typedef struct pte pte_t;
 /* RPN mask, TLB0 4K pages */
 #define PTE_PA_MASK	PAGE_MASK
 
+#if defined(BOOKE_E500)
+
 /* PTE bits assigned to MAS2, MAS3 flags */
 #define PTE_W		MAS2_W
 #define PTE_I		MAS2_I
@@ -241,6 +243,26 @@ typedef struct pte pte_t;
 #define PTE_MAS3_MASK	((MAS3_UX | MAS3_SX | MAS3_UW	\
 			| MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT)
 
+#elif defined(BOOKE_PPC4XX)
+
+#define PTE_WL1		TLB_WL1
+#define PTE_IL2I	TLB_IL2I
+#define PTE_IL2D	TLB_IL2D
+
+#define PTE_W		TLB_W
+#define PTE_I		TLB_I
+#define PTE_M		TLB_M
+#define PTE_G		TLB_G
+
+#define PTE_UX		TLB_UX
+#define PTE_SX		TLB_SX
+#define PTE_UW		TLB_UW
+#define PTE_SW		TLB_SW
+#define PTE_UR		TLB_UR
+#define PTE_SR		TLB_SR
+
+#endif
+
 /* Other PTE flags */
 #define PTE_VALID	0x80000000	/* Valid */
 #define PTE_MODIFIED	0x40000000	/* Modified */
@@ -256,6 +278,5 @@ typedef struct pte pte_t;
 #define PTE_ISMODIFIED(pte)	((pte)->flags & PTE_MODIFIED)
 #define PTE_ISREFERENCED(pte)	((pte)->flags & PTE_REFERENCED)
 
-#endif /* #elif defined(E500) */
-
+#endif /* BOOKE_PPC4XX */
 #endif /* _MACHINE_PTE_H_ */
diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h
index 6851c8a..79fad45 100644
--- a/sys/powerpc/include/spr.h
+++ b/sys/powerpc/include/spr.h
@@ -455,7 +455,7 @@
 #define	SPR_DAC1		0x3f6	/* 4.. Data Address Compare 1 */
 #define	SPR_DAC2		0x3f7	/* 4.. Data Address Compare 2 */
 #define	SPR_PIR			0x3ff	/* .6. Processor Identification Register */
-#elif defined(E500)
+#elif defined(BOOKE)
 #define	SPR_PIR			0x11e	/* ..8 Processor Identification Register */
 #define	SPR_DBSR		0x130	/* ..8 Debug Status Register */
 #define	  DBSR_IDE		  0x80000000 /* Imprecise debug event. */
@@ -628,7 +628,7 @@
 #define	  ESR_DIZ		  0x00800000 /* Data/instruction storage interrupt - zone fault */
 #define	  ESR_U0F		  0x00008000 /* Data storage interrupt - U0 fault */
 
-#elif defined(E500)
+#elif defined(BOOKE)
 
 #define	SPR_MCSR		0x23c	/* ..8 Machine Check Syndrome register */
 
@@ -642,12 +642,20 @@
 #define	  ESR_BO		  0x00020000 /* Data/instruction storage, byte ordering */
 #define	  ESR_SPE		  0x00000080 /* SPE exception bit */
 
-
 #define	SPR_CSRR0		0x03a	/* ..8 58 Critical SRR0 */
 #define	SPR_CSRR1		0x03b	/* ..8 59 Critical SRR1 */
 #define	SPR_MCSRR0		0x23a	/* ..8 570 Machine check SRR0 */
 #define	SPR_MCSRR1		0x23b	/* ..8 571 Machine check SRR1 */
 
+#define	SPR_MMUCR		0x3b2	/* 4.. MMU Control Register */
+#define	  MMUCR_SWOA		(0x80000000 >> 7)
+#define	  MMUCR_U1TE		(0x80000000 >> 9)
+#define	  MMUCR_U2SWOAE		(0x80000000 >> 10)
+#define	  MMUCR_DULXE		(0x80000000 >> 12)
+#define	  MMUCR_IULXE		(0x80000000 >> 13)
+#define	  MMUCR_STS		(0x80000000 >> 15)
+#define	  MMUCR_STID_MASK	(0xFF000000 >> 24)
+
 #define	SPR_MMUCSR0		0x3f4	/* ..8 1012 MMU Control and Status Register 0 */
 #define	  MMUCSR0_L2TLB0_FI	0x04	/*  TLB0 flash invalidate */
 #define	  MMUCSR0_L2TLB1_FI	0x02	/*  TLB1 flash invalidate */
@@ -758,6 +766,5 @@
 #define	  BUCSR_BPEN		0x00000001	/* Branch Prediction Enable */
 #define	  BUCSR_BBFI		0x00000200	/* Branch Buffer Flash Invalidate */
 
-#endif /* #elif defined(E500) */
-
+#endif /* BOOKE */
 #endif /* !_POWERPC_SPR_H_ */
diff --git a/sys/powerpc/include/tlb.h b/sys/powerpc/include/tlb.h
index 56f5521..7e0d909 100644
--- a/sys/powerpc/include/tlb.h
+++ b/sys/powerpc/include/tlb.h
@@ -1,5 +1,5 @@
 /*-
- * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
+ * Copyright (C) 2006-2012 Semihalf.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,6 +30,8 @@
 #ifndef	_MACHINE_TLB_H_
 #define	_MACHINE_TLB_H_
 
+#if defined(BOOKE_E500)
+
 /*  PowerPC E500 MAS registers */
 #define MAS0_TLBSEL(x)		((x << 28) & 0x10000000)
 #define MAS0_ESEL(x)		((x << 16) & 0x000F0000)
@@ -122,15 +124,6 @@
 #define _TLB_ENTRY_MEM	(0)
 #endif
 
-#define TID_KERNEL	0	/* TLB TID to use for kernel (shared) translations */
-#define TID_KRESERVED	1	/* Number of TIDs reserved for kernel */
-#define TID_URESERVED	0	/* Number of TIDs reserved for user */
-#define TID_MIN		(TID_KRESERVED + TID_URESERVED)
-#define TID_MAX		255
-#define TID_NONE	-1
-
-#define TLB_UNLOCKED	0
-
 #if !defined(LOCORE)
 typedef struct tlb_entry {
 	uint32_t mas1;
@@ -138,15 +131,80 @@ typedef struct tlb_entry {
 	uint32_t mas3;
 } tlb_entry_t;
 
-typedef int tlbtid_t;
-struct pmap;
-
 void tlb0_print_tlbentries(void);
 
 void tlb1_inval_entry(unsigned int);
 void tlb1_init(vm_offset_t);
 void tlb1_print_entries(void);
 void tlb1_print_tlbentries(void);
+#endif /* !LOCORE */
+
+#elif defined(BOOKE_PPC4XX)
+
+/* TLB Words */
+#define	TLB_PAGEID		0
+#define	TLB_XLAT		1
+#define	TLB_ATTRIB		2
+
+/* Page identification fields */
+#define	TLB_EPN_MASK		(0xFFFFFC00 >> 0)
+#define	TLB_VALID		(0x80000000 >> 22)
+#define	TLB_TS			(0x80000000 >> 23)
+#define	TLB_SIZE_1K		(0x00000000 >> 24)
+#define	TLB_SIZE_MASK		(0xF0000000 >> 24)
+
+/* Translation fields */
+#define	TLB_RPN_MASK		(0xFFFFFC00 >> 0)
+#define	TLB_ERPN_MASK		(0xF0000000 >> 28)
+
+/* Storage attribute and access control fields */
+#define	TLB_WL1			(0x80000000 >> 11)
+#define	TLB_IL1I		(0x80000000 >> 12)
+#define	TLB_IL1D		(0x80000000 >> 13)
+#define	TLB_IL2I		(0x80000000 >> 14)
+#define	TLB_IL2D		(0x80000000 >> 15)
+#define	TLB_U0			(0x80000000 >> 16)
+#define	TLB_U1			(0x80000000 >> 17)
+#define	TLB_U2			(0x80000000 >> 18)
+#define	TLB_U3			(0x80000000 >> 19)
+#define	TLB_W			(0x80000000 >> 20)
+#define	TLB_I			(0x80000000 >> 21)
+#define	TLB_M			(0x80000000 >> 22)
+#define	TLB_G			(0x80000000 >> 23)
+#define	TLB_E			(0x80000000 >> 24)
+#define	TLB_UX			(0x80000000 >> 26)
+#define	TLB_UW			(0x80000000 >> 27)
+#define	TLB_UR			(0x80000000 >> 28)
+#define	TLB_SX			(0x80000000 >> 29)
+#define	TLB_SW			(0x80000000 >> 30)
+#define	TLB_SR			(0x80000000 >> 31)
+#define	TLB_SIZE		64
+
+#define	TLB_SIZE_4K		(0x10000000 >> 24)
+#define	TLB_SIZE_16K		(0x20000000 >> 24)
+#define	TLB_SIZE_64K		(0x30000000 >> 24)
+#define	TLB_SIZE_256K		(0x40000000 >> 24)
+#define	TLB_SIZE_1M		(0x50000000 >> 24)
+#define	TLB_SIZE_16M		(0x70000000 >> 24)
+#define	TLB_SIZE_256M		(0x90000000 >> 24)
+#define	TLB_SIZE_1G		(0xA0000000 >> 24)
+
+#endif /* BOOKE_E500 */
+
+#define TID_KERNEL	0	/* TLB TID to use for kernel (shared) translations */
+#define TID_KRESERVED	1	/* Number of TIDs reserved for kernel */
+#define TID_URESERVED	0	/* Number of TIDs reserved for user */
+#define TID_MIN		(TID_KRESERVED + TID_URESERVED)
+#define TID_MAX		255
+#define TID_NONE	-1
+
+#define TLB_UNLOCKED	0
+
+#if !defined(LOCORE)
+
+typedef int tlbtid_t;
+
+struct pmap;
 
 void tlb_lock(uint32_t *);
 void tlb_unlock(uint32_t *);
diff --git a/sys/powerpc/include/trap.h b/sys/powerpc/include/trap.h
index 61543b4..75accf3 100644
--- a/sys/powerpc/include/trap.h
+++ b/sys/powerpc/include/trap.h
@@ -2,7 +2,7 @@
 
 #if defined(AIM)
 #include <machine/trap_aim.h>
-#elif defined(E500)
+#elif defined(BOOKE)
 #include <machine/trap_booke.h>
 #endif
 
diff --git a/sys/powerpc/include/vmparam.h b/sys/powerpc/include/vmparam.h
index 36afd1f..8368a41 100644
--- a/sys/powerpc/include/vmparam.h
+++ b/sys/powerpc/include/vmparam.h
@@ -78,7 +78,7 @@
 #endif
 #define	SHAREDPAGE		(VM_MAXUSER_ADDRESS - PAGE_SIZE)
 #else /* LOCORE */
-#if !defined(__powerpc64__) && defined(E500)
+#if !defined(__powerpc64__) && defined(BOOKE)
 #define	VM_MIN_ADDRESS		0
 #define	VM_MAXUSER_ADDRESS	0x7ffff000
 #endif