Fix final bugs in memory barriers on PowerPC:

- Use isync/lwsync unconditionally for acquire/release. Use of isync
  guarantees a complete memory barrier, which is important for serialization
  of bus space accesses with mutexes on multi-processor systems.
- Go back to using sync as the I/O memory barrier, which solves the same
  problem as above with respect to mutex release using lwsync, while not
  penalizing non-I/O operations like a return to sync on the atomic release
  operations would.
- Place an acquisition barrier around thread lock acquisition in
  cpu_switchin().

2 files changed, 6 insertions, 6 deletions

diff --git a/sys/powerpc/include/atomic.h b/sys/powerpc/include/atomic.h
index c88c3fa..8ec3ea0 100644
--- a/sys/powerpc/include/atomic.h
+++ b/sys/powerpc/include/atomic.h
@@ -51,13 +51,8 @@
  * with the atomic lXarx/stXcx. sequences below. See Appendix B.2 of Book II
  * of the architecture manual.
  */
-#ifdef __powerpc64__
-#define __ATOMIC_REL()	__asm __volatile("lwsync" : : : "memory")
-#define __ATOMIC_ACQ()	__asm __volatile("lwsync" : : : "memory")
-#else
 #define __ATOMIC_REL()	__asm __volatile("lwsync" : : : "memory")
 #define __ATOMIC_ACQ()	__asm __volatile("isync" : : : "memory")
-#endif
 
 /*
  * atomic_add(p, v)
diff --git a/sys/powerpc/include/pio.h b/sys/powerpc/include/pio.h
index 0994ed1..b09e68a 100644
--- a/sys/powerpc/include/pio.h
+++ b/sys/powerpc/include/pio.h
@@ -39,7 +39,12 @@
  * I/O macros.
  */
 
-#define powerpc_iomb() __asm __volatile("eieio" : : : "memory")
+/*
+ * Use sync so that bus space operations cannot sneak out the bottom of
+ * mutex-protected sections (mutex release does not guarantee completion of
+ * accesses to caching-inhibited memory on some systems)
+ */
+#define powerpc_iomb() __asm __volatile("sync" : : : "memory")
 
 static __inline void
 __outb(volatile u_int8_t *a, u_int8_t v)