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| author | raj <raj@FreeBSD.org> | 2012-05-27 10:25:20 +0000 |
|---|---|---|
| committer | raj <raj@FreeBSD.org> | 2012-05-27 10:25:20 +0000 |
| commit | 7136f7f8939dcacc1f3771052532a645cda85c8e (patch) | |
| tree | 0a8caf2cc24064494727a70f11cef5cc83610bdd /sys/powerpc/booke | |
| parent | 241db0ddf58e646306b00c95580c8115427707a5 (diff) | |
| download | FreeBSD-src-7136f7f8939dcacc1f3771052532a645cda85c8e.zip FreeBSD-src-7136f7f8939dcacc1f3771052532a645cda85c8e.tar.gz | |
Let us manage differences of Book-E PowerPC variations i.e. vendor /
implementation specific vs. the common architecture definition.
Bring PPC4XX defines (PSL, SPR, TLB). Note the new definitions under
BOOKE_PPC4XX are not used in the code yet.
This change set is not supposed to affect existing E500 support, it's just
another reorg step before bringing support for E500mc, E5500 and PPC465.
Obtained from: AppliedMicro, Freescale, Semihalf
Diffstat (limited to 'sys/powerpc/booke')
| -rw-r--r-- | sys/powerpc/booke/locore.S | 2 | ||||
| -rw-r--r-- | sys/powerpc/booke/machdep.c | 6 |
2 files changed, 7 insertions, 1 deletions
diff --git a/sys/powerpc/booke/locore.S b/sys/powerpc/booke/locore.S index 0255677..16a9196 100644 --- a/sys/powerpc/booke/locore.S +++ b/sys/powerpc/booke/locore.S @@ -218,7 +218,7 @@ done_mapping: mr %r3, %r30 mr %r4, %r31 - /* Prepare e500 core */ + /* Prepare core */ bl booke_init /* Switch to thread0.td_kstack now */ diff --git a/sys/powerpc/booke/machdep.c b/sys/powerpc/booke/machdep.c index 436cf06..09377fe 100644 --- a/sys/powerpc/booke/machdep.c +++ b/sys/powerpc/booke/machdep.c @@ -392,6 +392,7 @@ booke_init(uint32_t arg1, uint32_t arg2) debugf(" boothowto = 0x%08x\n", boothowto); debugf(" kernel ccsrbar = 0x%08x\n", CCSRBAR_VA); debugf(" MSR = 0x%08x\n", mfmsr()); +#if defined(BOOKE_E500) debugf(" HID0 = 0x%08x\n", mfspr(SPR_HID0)); debugf(" HID1 = 0x%08x\n", mfspr(SPR_HID1)); debugf(" BUCSR = 0x%08x\n", mfspr(SPR_BUCSR)); @@ -399,13 +400,16 @@ booke_init(uint32_t arg1, uint32_t arg2) __asm __volatile("msync; isync"); csr = ccsr_read4(OCP85XX_L2CTL); debugf(" L2CTL = 0x%08x\n", csr); +#endif debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp); print_kernel_section_addr(); print_kenv(); +#if defined(BOOKE_E500) //tlb1_print_entries(); //tlb1_print_tlbentries(); +#endif kdb_init(); @@ -421,8 +425,10 @@ booke_init(uint32_t arg1, uint32_t arg2) pmap_mmu_install(MMU_TYPE_BOOKE, 0); pmap_bootstrap((uintptr_t)kernel_text, end); debugf("MSR = 0x%08x\n", mfmsr()); +#if defined(BOOKE_E500) //tlb1_print_entries(); //tlb1_print_tlbentries(); +#endif /* Initialize params/tunables that are derived from memsize. */ init_param2(physmem); |
