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| author | jhibbits <jhibbits@FreeBSD.org> | 2014-01-15 06:17:15 +0000 |
|---|---|---|
| committer | jhibbits <jhibbits@FreeBSD.org> | 2014-01-15 06:17:15 +0000 |
| commit | 0920d1cd65aba877ec09c0e809f6d9b9def4b843 (patch) | |
| tree | 068d7235437a42e2f4e904d0610cb7b341058838 /sys/powerpc/aim | |
| parent | 876be05179ee42f81786351cda007d01cc994a03 (diff) | |
| download | FreeBSD-src-0920d1cd65aba877ec09c0e809f6d9b9def4b843.zip FreeBSD-src-0920d1cd65aba877ec09c0e809f6d9b9def4b843.tar.gz | |
MFC r259284,r259287
Add PMU-based CPU frequency scalling. This is used on most Titanium
PowerBooks.
Diffstat (limited to 'sys/powerpc/aim')
| -rw-r--r-- | sys/powerpc/aim/mp_cpudep.c | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/sys/powerpc/aim/mp_cpudep.c b/sys/powerpc/aim/mp_cpudep.c index 607256c..3fcab83 100644 --- a/sys/powerpc/aim/mp_cpudep.c +++ b/sys/powerpc/aim/mp_cpudep.c @@ -322,17 +322,13 @@ cpudep_ap_setup() mtspr(SPR_CELL_TSRL, bsp_state[5]); break; - case MPC7450: - case MPC7455: - case MPC7457: - /* Only MPC745x CPUs have an L3 cache. */ - reg = mpc745x_l3_enable(bsp_state[3]); - - /* Fallthrough */ case MPC7400: case MPC7410: case MPC7447A: case MPC7448: + case MPC7450: + case MPC7455: + case MPC7457: /* XXX: Program the CPU ID into PIR */ __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid))); @@ -342,6 +338,17 @@ cpudep_ap_setup() mtspr(SPR_HID0, bsp_state[0]); isync(); mtspr(SPR_HID1, bsp_state[1]); isync(); + /* Now enable the L3 cache. */ + switch (vers) { + case MPC7450: + case MPC7455: + case MPC7457: + /* Only MPC745x CPUs have an L3 cache. */ + reg = mpc745x_l3_enable(bsp_state[3]); + default: + break; + } + reg = mpc74xx_l2_enable(bsp_state[2]); reg = mpc74xx_l1d_enable(); reg = mpc74xx_l1i_enable(); |
