Move wb driver from sys/pci to sys/dev/wb.

2 files changed, 0 insertions, 2312 deletions

diff --git a/sys/pci/if_wb.c b/sys/pci/if_wb.c
deleted file mode 100644
index b652d6d..0000000
--- a/sys/pci/if_wb.c
+++ /dev/null
@@ -1,1848 +0,0 @@
-/*-
- * Copyright (c) 1997, 1998
- *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Bill Paul.
- * 4. Neither the name of the author nor the names of any co-contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-/*
- * Winbond fast ethernet PCI NIC driver
- *
- * Supports various cheap network adapters based on the Winbond W89C840F
- * fast ethernet controller chip. This includes adapters manufactured by
- * Winbond itself and some made by Linksys.
- *
- * Written by Bill Paul <wpaul@ctr.columbia.edu>
- * Electrical Engineering Department
- * Columbia University, New York City
- */
-/*
- * The Winbond W89C840F chip is a bus master; in some ways it resembles
- * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
- * one major difference which is that while the registers do many of
- * the same things as a tulip adapter, the offsets are different: where
- * tulip registers are typically spaced 8 bytes apart, the Winbond
- * registers are spaced 4 bytes apart. The receiver filter is also
- * programmed differently.
- * 
- * Like the tulip, the Winbond chip uses small descriptors containing
- * a status word, a control word and 32-bit areas that can either be used
- * to point to two external data blocks, or to point to a single block
- * and another descriptor in a linked list. Descriptors can be grouped
- * together in blocks to form fixed length rings or can be chained
- * together in linked lists. A single packet may be spread out over
- * several descriptors if necessary.
- *
- * For the receive ring, this driver uses a linked list of descriptors,
- * each pointing to a single mbuf cluster buffer, which us large enough
- * to hold an entire packet. The link list is looped back to created a
- * closed ring.
- *
- * For transmission, the driver creates a linked list of 'super descriptors'
- * which each contain several individual descriptors linked toghether.
- * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
- * abuse as fragment pointers. This allows us to use a buffer managment
- * scheme very similar to that used in the ThunderLAN and Etherlink XL
- * drivers.
- *
- * Autonegotiation is performed using the external PHY via the MII bus.
- * The sample boards I have all use a Davicom PHY.
- *
- * Note: the author of the Linux driver for the Winbond chip alludes
- * to some sort of flaw in the chip's design that seems to mandate some
- * drastic workaround which signigicantly impairs transmit performance.
- * I have no idea what he's on about: transmit performance with all
- * three of my test boards seems fine.
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/sockio.h>
-#include <sys/mbuf.h>
-#include <sys/malloc.h>
-#include <sys/module.h>
-#include <sys/kernel.h>
-#include <sys/socket.h>
-#include <sys/queue.h>
-
-#include <net/if.h>
-#include <net/if_arp.h>
-#include <net/ethernet.h>
-#include <net/if_dl.h>
-#include <net/if_media.h>
-#include <net/if_types.h>
-
-#include <net/bpf.h>
-
-#include <vm/vm.h>              /* for vtophys */
-#include <vm/pmap.h>            /* for vtophys */
-#include <machine/bus.h>
-#include <machine/resource.h>
-#include <sys/bus.h>
-#include <sys/rman.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#include <dev/mii/mii.h>
-#include <dev/mii/miivar.h>
-
-/* "device miibus" required.  See GENERIC if you get errors here. */
-#include "miibus_if.h"
-
-#define WB_USEIOSPACE
-
-#include <pci/if_wbreg.h>
-
-MODULE_DEPEND(wb, pci, 1, 1, 1);
-MODULE_DEPEND(wb, ether, 1, 1, 1);
-MODULE_DEPEND(wb, miibus, 1, 1, 1);
-
-/*
- * Various supported device vendors/types and their names.
- */
-static struct wb_type wb_devs[] = {
-	{ WB_VENDORID, WB_DEVICEID_840F,
-		"Winbond W89C840F 10/100BaseTX" },
-	{ CP_VENDORID, CP_DEVICEID_RL100,
-		"Compex RL100-ATX 10/100baseTX" },
-	{ 0, 0, NULL }
-};
-
-static int wb_probe(device_t);
-static int wb_attach(device_t);
-static int wb_detach(device_t);
-
-static void wb_bfree(void *addr, void *args);
-static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
-		struct mbuf *);
-static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
-
-static void wb_rxeof(struct wb_softc *);
-static void wb_rxeoc(struct wb_softc *);
-static void wb_txeof(struct wb_softc *);
-static void wb_txeoc(struct wb_softc *);
-static void wb_intr(void *);
-static void wb_tick(void *);
-static void wb_start(struct ifnet *);
-static void wb_start_locked(struct ifnet *);
-static int wb_ioctl(struct ifnet *, u_long, caddr_t);
-static void wb_init(void *);
-static void wb_init_locked(struct wb_softc *);
-static void wb_stop(struct wb_softc *);
-static void wb_watchdog(struct ifnet *);
-static void wb_shutdown(device_t);
-static int wb_ifmedia_upd(struct ifnet *);
-static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
-
-static void wb_eeprom_putbyte(struct wb_softc *, int);
-static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
-static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
-static void wb_mii_sync(struct wb_softc *);
-static void wb_mii_send(struct wb_softc *, u_int32_t, int);
-static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
-static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
-
-static void wb_setcfg(struct wb_softc *, u_int32_t);
-static void wb_setmulti(struct wb_softc *);
-static void wb_reset(struct wb_softc *);
-static void wb_fixmedia(struct wb_softc *);
-static int wb_list_rx_init(struct wb_softc *);
-static int wb_list_tx_init(struct wb_softc *);
-
-static int wb_miibus_readreg(device_t, int, int);
-static int wb_miibus_writereg(device_t, int, int, int);
-static void wb_miibus_statchg(device_t);
-
-#ifdef WB_USEIOSPACE
-#define WB_RES			SYS_RES_IOPORT
-#define WB_RID			WB_PCI_LOIO
-#else
-#define WB_RES			SYS_RES_MEMORY
-#define WB_RID			WB_PCI_LOMEM
-#endif
-
-static device_method_t wb_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		wb_probe),
-	DEVMETHOD(device_attach,	wb_attach),
-	DEVMETHOD(device_detach,	wb_detach),
-	DEVMETHOD(device_shutdown,	wb_shutdown),
-
-	/* bus interface, for miibus */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
-
-	/* MII interface */
-	DEVMETHOD(miibus_readreg,	wb_miibus_readreg),
-	DEVMETHOD(miibus_writereg,	wb_miibus_writereg),
-	DEVMETHOD(miibus_statchg,	wb_miibus_statchg),
-	{ 0, 0 }
-};
-
-static driver_t wb_driver = {
-	"wb",
-	wb_methods,
-	sizeof(struct wb_softc)
-};
-
-static devclass_t wb_devclass;
-
-DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
-DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
-
-#define WB_SETBIT(sc, reg, x)				\
-	CSR_WRITE_4(sc, reg,				\
-		CSR_READ_4(sc, reg) | (x))
-
-#define WB_CLRBIT(sc, reg, x)				\
-	CSR_WRITE_4(sc, reg,				\
-		CSR_READ_4(sc, reg) & ~(x))
-
-#define SIO_SET(x)					\
-	CSR_WRITE_4(sc, WB_SIO,				\
-		CSR_READ_4(sc, WB_SIO) | (x))
-
-#define SIO_CLR(x)					\
-	CSR_WRITE_4(sc, WB_SIO,				\
-		CSR_READ_4(sc, WB_SIO) & ~(x))
-
-/*
- * Send a read command and address to the EEPROM, check for ACK.
- */
-static void
-wb_eeprom_putbyte(sc, addr)
-	struct wb_softc		*sc;
-	int			addr;
-{
-	register int		d, i;
-
-	d = addr | WB_EECMD_READ;
-
-	/*
-	 * Feed in each bit and stobe the clock.
-	 */
-	for (i = 0x400; i; i >>= 1) {
-		if (d & i) {
-			SIO_SET(WB_SIO_EE_DATAIN);
-		} else {
-			SIO_CLR(WB_SIO_EE_DATAIN);
-		}
-		DELAY(100);
-		SIO_SET(WB_SIO_EE_CLK);
-		DELAY(150);
-		SIO_CLR(WB_SIO_EE_CLK);
-		DELAY(100);
-	}
-
-	return;
-}
-
-/*
- * Read a word of data stored in the EEPROM at address 'addr.'
- */
-static void
-wb_eeprom_getword(sc, addr, dest)
-	struct wb_softc		*sc;
-	int			addr;
-	u_int16_t		*dest;
-{
-	register int		i;
-	u_int16_t		word = 0;
-
-	/* Enter EEPROM access mode. */
-	CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
-
-	/*
-	 * Send address of word we want to read.
-	 */
-	wb_eeprom_putbyte(sc, addr);
-
-	CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
-
-	/*
-	 * Start reading bits from EEPROM.
-	 */
-	for (i = 0x8000; i; i >>= 1) {
-		SIO_SET(WB_SIO_EE_CLK);
-		DELAY(100);
-		if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
-			word |= i;
-		SIO_CLR(WB_SIO_EE_CLK);
-		DELAY(100);
-	}
-
-	/* Turn off EEPROM access mode. */
-	CSR_WRITE_4(sc, WB_SIO, 0);
-
-	*dest = word;
-
-	return;
-}
-
-/*
- * Read a sequence of words from the EEPROM.
- */
-static void
-wb_read_eeprom(sc, dest, off, cnt, swap)
-	struct wb_softc		*sc;
-	caddr_t			dest;
-	int			off;
-	int			cnt;
-	int			swap;
-{
-	int			i;
-	u_int16_t		word = 0, *ptr;
-
-	for (i = 0; i < cnt; i++) {
-		wb_eeprom_getword(sc, off + i, &word);
-		ptr = (u_int16_t *)(dest + (i * 2));
-		if (swap)
-			*ptr = ntohs(word);
-		else
-			*ptr = word;
-	}
-
-	return;
-}
-
-/*
- * Sync the PHYs by setting data bit and strobing the clock 32 times.
- */
-static void
-wb_mii_sync(sc)
-	struct wb_softc		*sc;
-{
-	register int		i;
-
-	SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
-
-	for (i = 0; i < 32; i++) {
-		SIO_SET(WB_SIO_MII_CLK);
-		DELAY(1);
-		SIO_CLR(WB_SIO_MII_CLK);
-		DELAY(1);
-	}
-
-	return;
-}
-
-/*
- * Clock a series of bits through the MII.
- */
-static void
-wb_mii_send(sc, bits, cnt)
-	struct wb_softc		*sc;
-	u_int32_t		bits;
-	int			cnt;
-{
-	int			i;
-
-	SIO_CLR(WB_SIO_MII_CLK);
-
-	for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
-                if (bits & i) {
-			SIO_SET(WB_SIO_MII_DATAIN);
-                } else {
-			SIO_CLR(WB_SIO_MII_DATAIN);
-                }
-		DELAY(1);
-		SIO_CLR(WB_SIO_MII_CLK);
-		DELAY(1);
-		SIO_SET(WB_SIO_MII_CLK);
-	}
-}
-
-/*
- * Read an PHY register through the MII.
- */
-static int
-wb_mii_readreg(sc, frame)
-	struct wb_softc		*sc;
-	struct wb_mii_frame	*frame;
-	
-{
-	int			i, ack;
-
-	/*
-	 * Set up frame for RX.
-	 */
-	frame->mii_stdelim = WB_MII_STARTDELIM;
-	frame->mii_opcode = WB_MII_READOP;
-	frame->mii_turnaround = 0;
-	frame->mii_data = 0;
-	
-	CSR_WRITE_4(sc, WB_SIO, 0);
-
-	/*
- 	 * Turn on data xmit.
-	 */
-	SIO_SET(WB_SIO_MII_DIR);
-
-	wb_mii_sync(sc);
-
-	/*
-	 * Send command/address info.
-	 */
-	wb_mii_send(sc, frame->mii_stdelim, 2);
-	wb_mii_send(sc, frame->mii_opcode, 2);
-	wb_mii_send(sc, frame->mii_phyaddr, 5);
-	wb_mii_send(sc, frame->mii_regaddr, 5);
-
-	/* Idle bit */
-	SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
-	DELAY(1);
-	SIO_SET(WB_SIO_MII_CLK);
-	DELAY(1);
-
-	/* Turn off xmit. */
-	SIO_CLR(WB_SIO_MII_DIR);
-	/* Check for ack */
-	SIO_CLR(WB_SIO_MII_CLK);
-	DELAY(1);
-	ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
-	SIO_SET(WB_SIO_MII_CLK);
-	DELAY(1);
-	SIO_CLR(WB_SIO_MII_CLK);
-	DELAY(1);
-	SIO_SET(WB_SIO_MII_CLK);
-	DELAY(1);
-
-	/*
-	 * Now try reading data bits. If the ack failed, we still
-	 * need to clock through 16 cycles to keep the PHY(s) in sync.
-	 */
-	if (ack) {
-		for(i = 0; i < 16; i++) {
-			SIO_CLR(WB_SIO_MII_CLK);
-			DELAY(1);
-			SIO_SET(WB_SIO_MII_CLK);
-			DELAY(1);
-		}
-		goto fail;
-	}
-
-	for (i = 0x8000; i; i >>= 1) {
-		SIO_CLR(WB_SIO_MII_CLK);
-		DELAY(1);
-		if (!ack) {
-			if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
-				frame->mii_data |= i;
-			DELAY(1);
-		}
-		SIO_SET(WB_SIO_MII_CLK);
-		DELAY(1);
-	}
-
-fail:
-
-	SIO_CLR(WB_SIO_MII_CLK);
-	DELAY(1);
-	SIO_SET(WB_SIO_MII_CLK);
-	DELAY(1);
-
-	if (ack)
-		return(1);
-	return(0);
-}
-
-/*
- * Write to a PHY register through the MII.
- */
-static int
-wb_mii_writereg(sc, frame)
-	struct wb_softc		*sc;
-	struct wb_mii_frame	*frame;
-	
-{
-
-	/*
-	 * Set up frame for TX.
-	 */
-
-	frame->mii_stdelim = WB_MII_STARTDELIM;
-	frame->mii_opcode = WB_MII_WRITEOP;
-	frame->mii_turnaround = WB_MII_TURNAROUND;
-	
-	/*
- 	 * Turn on data output.
-	 */
-	SIO_SET(WB_SIO_MII_DIR);
-
-	wb_mii_sync(sc);
-
-	wb_mii_send(sc, frame->mii_stdelim, 2);
-	wb_mii_send(sc, frame->mii_opcode, 2);
-	wb_mii_send(sc, frame->mii_phyaddr, 5);
-	wb_mii_send(sc, frame->mii_regaddr, 5);
-	wb_mii_send(sc, frame->mii_turnaround, 2);
-	wb_mii_send(sc, frame->mii_data, 16);
-
-	/* Idle bit. */
-	SIO_SET(WB_SIO_MII_CLK);
-	DELAY(1);
-	SIO_CLR(WB_SIO_MII_CLK);
-	DELAY(1);
-
-	/*
-	 * Turn off xmit.
-	 */
-	SIO_CLR(WB_SIO_MII_DIR);
-
-	return(0);
-}
-
-static int
-wb_miibus_readreg(dev, phy, reg)
-	device_t		dev;
-	int			phy, reg;
-{
-	struct wb_softc		*sc;
-	struct wb_mii_frame	frame;
-
-	sc = device_get_softc(dev);
-
-	bzero((char *)&frame, sizeof(frame));
-
-	frame.mii_phyaddr = phy;
-	frame.mii_regaddr = reg;
-	wb_mii_readreg(sc, &frame);
-
-	return(frame.mii_data);
-}
-
-static int
-wb_miibus_writereg(dev, phy, reg, data)
-	device_t		dev;
-	int			phy, reg, data;
-{
-	struct wb_softc		*sc;
-	struct wb_mii_frame	frame;
-
-	sc = device_get_softc(dev);
-
-	bzero((char *)&frame, sizeof(frame));
-
-	frame.mii_phyaddr = phy;
-	frame.mii_regaddr = reg;
-	frame.mii_data = data;
-
-	wb_mii_writereg(sc, &frame);
-
-	return(0);
-}
-
-static void
-wb_miibus_statchg(dev)
-	device_t		dev;
-{
-	struct wb_softc		*sc;
-	struct mii_data		*mii;
-
-	sc = device_get_softc(dev);
-	mii = device_get_softc(sc->wb_miibus);
-	wb_setcfg(sc, mii->mii_media_active);
-
-	return;
-}
-
-/*
- * Program the 64-bit multicast hash filter.
- */
-static void
-wb_setmulti(sc)
-	struct wb_softc		*sc;
-{
-	struct ifnet		*ifp;
-	int			h = 0;
-	u_int32_t		hashes[2] = { 0, 0 };
-	struct ifmultiaddr	*ifma;
-	u_int32_t		rxfilt;
-	int			mcnt = 0;
-
-	ifp = sc->wb_ifp;
-
-	rxfilt = CSR_READ_4(sc, WB_NETCFG);
-
-	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
-		rxfilt |= WB_NETCFG_RX_MULTI;
-		CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
-		CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
-		CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
-		return;
-	}
-
-	/* first, zot all the existing hash bits */
-	CSR_WRITE_4(sc, WB_MAR0, 0);
-	CSR_WRITE_4(sc, WB_MAR1, 0);
-
-	/* now program new ones */
-	IF_ADDR_LOCK(ifp);
-	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
-		if (ifma->ifma_addr->sa_family != AF_LINK)
-			continue;
-		h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
-		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
-		if (h < 32)
-			hashes[0] |= (1 << h);
-		else
-			hashes[1] |= (1 << (h - 32));
-		mcnt++;
-	}
-	IF_ADDR_UNLOCK(ifp);
-
-	if (mcnt)
-		rxfilt |= WB_NETCFG_RX_MULTI;
-	else
-		rxfilt &= ~WB_NETCFG_RX_MULTI;
-
-	CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
-	CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
-	CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
-
-	return;
-}
-
-/*
- * The Winbond manual states that in order to fiddle with the
- * 'full-duplex' and '100Mbps' bits in the netconfig register, we
- * first have to put the transmit and/or receive logic in the idle state.
- */
-static void
-wb_setcfg(sc, media)
-	struct wb_softc		*sc;
-	u_int32_t		media;
-{
-	int			i, restart = 0;
-
-	if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
-		restart = 1;
-		WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
-
-		for (i = 0; i < WB_TIMEOUT; i++) {
-			DELAY(10);
-			if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
-				(CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
-				break;
-		}
-
-		if (i == WB_TIMEOUT)
-			device_printf(sc->wb_dev,
-			    "failed to force tx and rx to idle state\n");
-	}
-
-	if (IFM_SUBTYPE(media) == IFM_10_T)
-		WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
-	else
-		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
-
-	if ((media & IFM_GMASK) == IFM_FDX)
-		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
-	else
-		WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
-
-	if (restart)
-		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
-
-	return;
-}
-
-static void
-wb_reset(sc)
-	struct wb_softc		*sc;
-{
-	register int		i;
-	struct mii_data		*mii;
-
-	CSR_WRITE_4(sc, WB_NETCFG, 0);
-	CSR_WRITE_4(sc, WB_BUSCTL, 0);
-	CSR_WRITE_4(sc, WB_TXADDR, 0);
-	CSR_WRITE_4(sc, WB_RXADDR, 0);
-
-	WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
-	WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
-
-	for (i = 0; i < WB_TIMEOUT; i++) {
-		DELAY(10);
-		if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
-			break;
-	}
-	if (i == WB_TIMEOUT)
-		device_printf(sc->wb_dev, "reset never completed!\n");
-
-	/* Wait a little while for the chip to get its brains in order. */
-	DELAY(1000);
-
-	if (sc->wb_miibus == NULL)
-		return;
-
-	mii = device_get_softc(sc->wb_miibus);
-	if (mii == NULL)
-		return;
-
-        if (mii->mii_instance) {
-                struct mii_softc        *miisc;
-                LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
-                        mii_phy_reset(miisc);
-        }
-
-        return;
-}
-
-static void
-wb_fixmedia(sc)
-	struct wb_softc		*sc;
-{
-	struct mii_data		*mii = NULL;
-	struct ifnet		*ifp;
-	u_int32_t		media;
-
-	if (sc->wb_miibus == NULL)
-		return;
-
-	mii = device_get_softc(sc->wb_miibus);
-	ifp = sc->wb_ifp;
-
-	mii_pollstat(mii);
-	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
-		media = mii->mii_media_active & ~IFM_10_T;
-		media |= IFM_100_TX;
-	} else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
-		media = mii->mii_media_active & ~IFM_100_TX;
-		media |= IFM_10_T;
-	} else
-		return;
-
-	ifmedia_set(&mii->mii_media, media);
-
-	return;
-}
-
-/*
- * Probe for a Winbond chip. Check the PCI vendor and device
- * IDs against our list and return a device name if we find a match.
- */
-static int
-wb_probe(dev)
-	device_t		dev;
-{
-	struct wb_type		*t;
-
-	t = wb_devs;
-
-	while(t->wb_name != NULL) {
-		if ((pci_get_vendor(dev) == t->wb_vid) &&
-		    (pci_get_device(dev) == t->wb_did)) {
-			device_set_desc(dev, t->wb_name);
-			return (BUS_PROBE_DEFAULT);
-		}
-		t++;
-	}
-
-	return(ENXIO);
-}
-
-/*
- * Attach the interface. Allocate softc structures, do ifmedia
- * setup and ethernet/BPF attach.
- */
-static int
-wb_attach(dev)
-	device_t		dev;
-{
-	u_char			eaddr[ETHER_ADDR_LEN];
-	struct wb_softc		*sc;
-	struct ifnet		*ifp;
-	int			error = 0, rid;
-
-	sc = device_get_softc(dev);
-	sc->wb_dev = dev;
-
-	mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
-	    MTX_DEF);
-	callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0);
-
-	/*
-	 * Map control/status registers.
-	 */
-	pci_enable_busmaster(dev);
-
-	rid = WB_RID;
-	sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
-
-	if (sc->wb_res == NULL) {
-		device_printf(dev, "couldn't map ports/memory\n");
-		error = ENXIO;
-		goto fail;
-	}
-
-	sc->wb_btag = rman_get_bustag(sc->wb_res);
-	sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
-
-	/* Allocate interrupt */
-	rid = 0;
-	sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
-	    RF_SHAREABLE | RF_ACTIVE);
-
-	if (sc->wb_irq == NULL) {
-		device_printf(dev, "couldn't map interrupt\n");
-		error = ENXIO;
-		goto fail;
-	}
-
-	/* Save the cache line size. */
-	sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
-
-	/* Reset the adapter. */
-	wb_reset(sc);
-
-	/*
-	 * Get station address from the EEPROM.
-	 */
-	wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
-
-	sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
-	    M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
-
-	if (sc->wb_ldata == NULL) {
-		device_printf(dev, "no memory for list buffers!\n");
-		error = ENXIO;
-		goto fail;
-	}
-
-	bzero(sc->wb_ldata, sizeof(struct wb_list_data));
-
-	ifp = sc->wb_ifp = if_alloc(IFT_ETHER);
-	if (ifp == NULL) {
-		device_printf(dev, "can not if_alloc()\n");
-		error = ENOSPC;
-		goto fail;
-	}
-	ifp->if_softc = sc;
-	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
-	ifp->if_mtu = ETHERMTU;
-	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
-	ifp->if_ioctl = wb_ioctl;
-	ifp->if_start = wb_start;
-	ifp->if_watchdog = wb_watchdog;
-	ifp->if_init = wb_init;
-	ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
-
-	/*
-	 * Do MII setup.
-	 */
-	if (mii_phy_probe(dev, &sc->wb_miibus,
-	    wb_ifmedia_upd, wb_ifmedia_sts)) {
-		error = ENXIO;
-		goto fail;
-	}
-
-	/*
-	 * Call MI attach routine.
-	 */
-	ether_ifattach(ifp, eaddr);
-
-	/* Hook interrupt last to avoid having to lock softc */
-	error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE,
-	    NULL, wb_intr, sc, &sc->wb_intrhand);
-
-	if (error) {
-		device_printf(dev, "couldn't set up irq\n");
-		ether_ifdetach(ifp);
-		goto fail;
-	}
-
-fail:
-	if (error)
-		wb_detach(dev);
-
-	return(error);
-}
-
-/*
- * Shutdown hardware and free up resources. This can be called any
- * time after the mutex has been initialized. It is called in both
- * the error case in attach and the normal detach case so it needs
- * to be careful about only freeing resources that have actually been
- * allocated.
- */
-static int
-wb_detach(dev)
-	device_t		dev;
-{
-	struct wb_softc		*sc;
-	struct ifnet		*ifp;
-
-	sc = device_get_softc(dev);
-	KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized"));
-	ifp = sc->wb_ifp;
-
-	/* 
-	 * Delete any miibus and phy devices attached to this interface.
-	 * This should only be done if attach succeeded.
-	 */
-	if (device_is_attached(dev)) {
-		WB_LOCK(sc);
-		wb_stop(sc);
-		WB_UNLOCK(sc);
-		callout_drain(&sc->wb_stat_callout);
-		ether_ifdetach(ifp);
-	}
-	if (sc->wb_miibus)
-		device_delete_child(dev, sc->wb_miibus);
-	bus_generic_detach(dev);
-
-	if (sc->wb_intrhand)
-		bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
-	if (sc->wb_irq)
-		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
-	if (sc->wb_res)
-		bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
-
-	if (ifp)
-		if_free(ifp);
-
-	if (sc->wb_ldata) {
-		contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8,
-		    M_DEVBUF);
-	}
-
-	mtx_destroy(&sc->wb_mtx);
-
-	return(0);
-}
-
-/*
- * Initialize the transmit descriptors.
- */
-static int
-wb_list_tx_init(sc)
-	struct wb_softc		*sc;
-{
-	struct wb_chain_data	*cd;
-	struct wb_list_data	*ld;
-	int			i;
-
-	cd = &sc->wb_cdata;
-	ld = sc->wb_ldata;
-
-	for (i = 0; i < WB_TX_LIST_CNT; i++) {
-		cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
-		if (i == (WB_TX_LIST_CNT - 1)) {
-			cd->wb_tx_chain[i].wb_nextdesc =
-				&cd->wb_tx_chain[0];
-		} else {
-			cd->wb_tx_chain[i].wb_nextdesc =
-				&cd->wb_tx_chain[i + 1];
-		}
-	}
-
-	cd->wb_tx_free = &cd->wb_tx_chain[0];
-	cd->wb_tx_tail = cd->wb_tx_head = NULL;
-
-	return(0);
-}
-
-
-/*
- * Initialize the RX descriptors and allocate mbufs for them. Note that
- * we arrange the descriptors in a closed ring, so that the last descriptor
- * points back to the first.
- */
-static int
-wb_list_rx_init(sc)
-	struct wb_softc		*sc;
-{
-	struct wb_chain_data	*cd;
-	struct wb_list_data	*ld;
-	int			i;
-
-	cd = &sc->wb_cdata;
-	ld = sc->wb_ldata;
-
-	for (i = 0; i < WB_RX_LIST_CNT; i++) {
-		cd->wb_rx_chain[i].wb_ptr =
-			(struct wb_desc *)&ld->wb_rx_list[i];
-		cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
-		if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
-			return(ENOBUFS);
-		if (i == (WB_RX_LIST_CNT - 1)) {
-			cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
-			ld->wb_rx_list[i].wb_next = 
-					vtophys(&ld->wb_rx_list[0]);
-		} else {
-			cd->wb_rx_chain[i].wb_nextdesc =
-					&cd->wb_rx_chain[i + 1];
-			ld->wb_rx_list[i].wb_next =
-					vtophys(&ld->wb_rx_list[i + 1]);
-		}
-	}
-
-	cd->wb_rx_head = &cd->wb_rx_chain[0];
-
-	return(0);
-}
-
-static void
-wb_bfree(buf, args)
-	void			*buf;
-	void			*args;
-{
-	return;
-}
-
-/*
- * Initialize an RX descriptor and attach an MBUF cluster.
- */
-static int
-wb_newbuf(sc, c, m)
-	struct wb_softc		*sc;
-	struct wb_chain_onefrag	*c;
-	struct mbuf		*m;
-{
-	struct mbuf		*m_new = NULL;
-
-	if (m == NULL) {
-		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
-		if (m_new == NULL)
-			return(ENOBUFS);
-		m_new->m_data = c->wb_buf;
-		m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES;
-		MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf,
-		    NULL, 0, EXT_NET_DRV);
-	} else {
-		m_new = m;
-		m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
-		m_new->m_data = m_new->m_ext.ext_buf;
-	}
-
-	m_adj(m_new, sizeof(u_int64_t));
-
-	c->wb_mbuf = m_new;
-	c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
-	c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
-	c->wb_ptr->wb_status = WB_RXSTAT;
-
-	return(0);
-}
-
-/*
- * A frame has been uploaded: pass the resulting mbuf chain up to
- * the higher level protocols.
- */
-static void
-wb_rxeof(sc)
-	struct wb_softc		*sc;
-{
-        struct mbuf		*m = NULL;
-        struct ifnet		*ifp;
-	struct wb_chain_onefrag	*cur_rx;
-	int			total_len = 0;
-	u_int32_t		rxstat;
-
-	WB_LOCK_ASSERT(sc);
-
-	ifp = sc->wb_ifp;
-
-	while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
-							WB_RXSTAT_OWN)) {
-		struct mbuf		*m0 = NULL;
-
-		cur_rx = sc->wb_cdata.wb_rx_head;
-		sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
-
-		m = cur_rx->wb_mbuf;
-
-		if ((rxstat & WB_RXSTAT_MIIERR) ||
-		    (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
-		    (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
-		    !(rxstat & WB_RXSTAT_LASTFRAG) ||
-		    !(rxstat & WB_RXSTAT_RXCMP)) {
-			ifp->if_ierrors++;
-			wb_newbuf(sc, cur_rx, m);
-			device_printf(sc->wb_dev,
-			    "receiver babbling: possible chip bug,"
-			    " forcing reset\n");
-			wb_fixmedia(sc);
-			wb_reset(sc);
-			wb_init_locked(sc);
-			return;
-		}
-
-		if (rxstat & WB_RXSTAT_RXERR) {
-			ifp->if_ierrors++;
-			wb_newbuf(sc, cur_rx, m);
-			break;
-		}
-
-		/* No errors; receive the packet. */	
-		total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
-
-		/*
-		 * XXX The Winbond chip includes the CRC with every
-		 * received frame, and there's no way to turn this
-		 * behavior off (at least, I can't find anything in
-	 	 * the manual that explains how to do it) so we have
-		 * to trim off the CRC manually.
-		 */
-		total_len -= ETHER_CRC_LEN;
-
-		m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
-		    NULL);
-		wb_newbuf(sc, cur_rx, m);
-		if (m0 == NULL) {
-			ifp->if_ierrors++;
-			break;
-		}
-		m = m0;
-
-		ifp->if_ipackets++;
-		WB_UNLOCK(sc);
-		(*ifp->if_input)(ifp, m);
-		WB_LOCK(sc);
-	}
-}
-
-static void
-wb_rxeoc(sc)
-	struct wb_softc		*sc;
-{
-	wb_rxeof(sc);
-
-	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
-	CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
-	WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
-	if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
-		CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
-
-	return;
-}
-
-/*
- * A frame was downloaded to the chip. It's safe for us to clean up
- * the list buffers.
- */
-static void
-wb_txeof(sc)
-	struct wb_softc		*sc;
-{
-	struct wb_chain		*cur_tx;
-	struct ifnet		*ifp;
-
-	ifp = sc->wb_ifp;
-
-	/* Clear the timeout timer. */
-	ifp->if_timer = 0;
-
-	if (sc->wb_cdata.wb_tx_head == NULL)
-		return;
-
-	/*
-	 * Go through our tx list and free mbufs for those
-	 * frames that have been transmitted.
-	 */
-	while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
-		u_int32_t		txstat;
-
-		cur_tx = sc->wb_cdata.wb_tx_head;
-		txstat = WB_TXSTATUS(cur_tx);
-
-		if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
-			break;
-
-		if (txstat & WB_TXSTAT_TXERR) {
-			ifp->if_oerrors++;
-			if (txstat & WB_TXSTAT_ABORT)
-				ifp->if_collisions++;
-			if (txstat & WB_TXSTAT_LATECOLL)
-				ifp->if_collisions++;
-		}
-
-		ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
-
-		ifp->if_opackets++;
-		m_freem(cur_tx->wb_mbuf);
-		cur_tx->wb_mbuf = NULL;
-
-		if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
-			sc->wb_cdata.wb_tx_head = NULL;
-			sc->wb_cdata.wb_tx_tail = NULL;
-			break;
-		}
-
-		sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
-	}
-
-	return;
-}
-
-/*
- * TX 'end of channel' interrupt handler.
- */
-static void
-wb_txeoc(sc)
-	struct wb_softc		*sc;
-{
-	struct ifnet		*ifp;
-
-	ifp = sc->wb_ifp;
-
-	ifp->if_timer = 0;
-
-	if (sc->wb_cdata.wb_tx_head == NULL) {
-		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
-		sc->wb_cdata.wb_tx_tail = NULL;
-	} else {
-		if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
-			WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
-			ifp->if_timer = 5;
-			CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
-		}
-	}
-
-	return;
-}
-
-static void
-wb_intr(arg)
-	void			*arg;
-{
-	struct wb_softc		*sc;
-	struct ifnet		*ifp;
-	u_int32_t		status;
-
-	sc = arg;
-	WB_LOCK(sc);
-	ifp = sc->wb_ifp;
-
-	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
-		WB_UNLOCK(sc);
-		return;
-	}
-
-	/* Disable interrupts. */
-	CSR_WRITE_4(sc, WB_IMR, 0x00000000);
-
-	for (;;) {
-
-		status = CSR_READ_4(sc, WB_ISR);
-		if (status)
-			CSR_WRITE_4(sc, WB_ISR, status);
-
-		if ((status & WB_INTRS) == 0)
-			break;
-
-		if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
-			ifp->if_ierrors++;
-			wb_reset(sc);
-			if (status & WB_ISR_RX_ERR)
-				wb_fixmedia(sc);
-			wb_init_locked(sc);
-			continue;
-		}
-
-		if (status & WB_ISR_RX_OK)
-			wb_rxeof(sc);
-	
-		if (status & WB_ISR_RX_IDLE)
-			wb_rxeoc(sc);
-
-		if (status & WB_ISR_TX_OK)
-			wb_txeof(sc);
-
-		if (status & WB_ISR_TX_NOBUF)
-			wb_txeoc(sc);
-
-		if (status & WB_ISR_TX_IDLE) {
-			wb_txeof(sc);
-			if (sc->wb_cdata.wb_tx_head != NULL) {
-				WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
-				CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
-			}
-		}
-
-		if (status & WB_ISR_TX_UNDERRUN) {
-			ifp->if_oerrors++;
-			wb_txeof(sc);
-			WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
-			/* Jack up TX threshold */
-			sc->wb_txthresh += WB_TXTHRESH_CHUNK;
-			WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
-			WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
-			WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
-		}
-
-		if (status & WB_ISR_BUS_ERR) {
-			wb_reset(sc);
-			wb_init_locked(sc);
-		}
-
-	}
-
-	/* Re-enable interrupts. */
-	CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
-
-	if (ifp->if_snd.ifq_head != NULL) {
-		wb_start_locked(ifp);
-	}
-
-	WB_UNLOCK(sc);
-
-	return;
-}
-
-static void
-wb_tick(xsc)
-	void			*xsc;
-{
-	struct wb_softc		*sc;
-	struct mii_data		*mii;
-
-	sc = xsc;
-	WB_LOCK_ASSERT(sc);
-	mii = device_get_softc(sc->wb_miibus);
-
-	mii_tick(mii);
-
-	callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
-
-	return;
-}
-
-/*
- * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
- * pointers to the fragment pointers.
- */
-static int
-wb_encap(sc, c, m_head)
-	struct wb_softc		*sc;
-	struct wb_chain		*c;
-	struct mbuf		*m_head;
-{
-	int			frag = 0;
-	struct wb_desc		*f = NULL;
-	int			total_len;
-	struct mbuf		*m;
-
-	/*
- 	 * Start packing the mbufs in this chain into
-	 * the fragment pointers. Stop when we run out
- 	 * of fragments or hit the end of the mbuf chain.
-	 */
-	m = m_head;
-	total_len = 0;
-
-	for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
-		if (m->m_len != 0) {
-			if (frag == WB_MAXFRAGS)
-				break;
-			total_len += m->m_len;
-			f = &c->wb_ptr->wb_frag[frag];
-			f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
-			if (frag == 0) {
-				f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
-				f->wb_status = 0;
-			} else
-				f->wb_status = WB_TXSTAT_OWN;
-			f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
-			f->wb_data = vtophys(mtod(m, vm_offset_t));
-			frag++;
-		}
-	}
-
-	/*
-	 * Handle special case: we used up all 16 fragments,
-	 * but we have more mbufs left in the chain. Copy the
-	 * data into an mbuf cluster. Note that we don't
-	 * bother clearing the values in the other fragment
-	 * pointers/counters; it wouldn't gain us anything,
-	 * and would waste cycles.
-	 */
-	if (m != NULL) {
-		struct mbuf		*m_new = NULL;
-
-		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
-		if (m_new == NULL)
-			return(1);
-		if (m_head->m_pkthdr.len > MHLEN) {
-			MCLGET(m_new, M_DONTWAIT);
-			if (!(m_new->m_flags & M_EXT)) {
-				m_freem(m_new);
-				return(1);
-			}
-		}
-		m_copydata(m_head, 0, m_head->m_pkthdr.len,	
-					mtod(m_new, caddr_t));
-		m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
-		m_freem(m_head);
-		m_head = m_new;
-		f = &c->wb_ptr->wb_frag[0];
-		f->wb_status = 0;
-		f->wb_data = vtophys(mtod(m_new, caddr_t));
-		f->wb_ctl = total_len = m_new->m_len;
-		f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
-		frag = 1;
-	}
-
-	if (total_len < WB_MIN_FRAMELEN) {
-		f = &c->wb_ptr->wb_frag[frag];
-		f->wb_ctl = WB_MIN_FRAMELEN - total_len;
-		f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
-		f->wb_ctl |= WB_TXCTL_TLINK;
-		f->wb_status = WB_TXSTAT_OWN;
-		frag++;
-	}
-
-	c->wb_mbuf = m_head;
-	c->wb_lastdesc = frag - 1;
-	WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
-	WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
-
-	return(0);
-}
-
-/*
- * Main transmit routine. To avoid having to do mbuf copies, we put pointers
- * to the mbuf data regions directly in the transmit lists. We also save a
- * copy of the pointers since the transmit list fragment pointers are
- * physical addresses.
- */
-
-static void
-wb_start(ifp)
-	struct ifnet		*ifp;
-{
-	struct wb_softc		*sc;
-
-	sc = ifp->if_softc;
-	WB_LOCK(sc);
-	wb_start_locked(ifp);
-	WB_UNLOCK(sc);
-}
-
-static void
-wb_start_locked(ifp)
-	struct ifnet		*ifp;
-{
-	struct wb_softc		*sc;
-	struct mbuf		*m_head = NULL;
-	struct wb_chain		*cur_tx = NULL, *start_tx;
-
-	sc = ifp->if_softc;
-	WB_LOCK_ASSERT(sc);
-
-	/*
-	 * Check for an available queue slot. If there are none,
-	 * punt.
-	 */
-	if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
-		ifp->if_drv_flags |= IFF_DRV_OACTIVE;
-		return;
-	}
-
-	start_tx = sc->wb_cdata.wb_tx_free;
-
-	while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
-		IF_DEQUEUE(&ifp->if_snd, m_head);
-		if (m_head == NULL)
-			break;
-
-		/* Pick a descriptor off the free list. */
-		cur_tx = sc->wb_cdata.wb_tx_free;
-		sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
-
-		/* Pack the data into the descriptor. */
-		wb_encap(sc, cur_tx, m_head);
-
-		if (cur_tx != start_tx)
-			WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
-
-		/*
-		 * If there's a BPF listener, bounce a copy of this frame
-		 * to him.
-		 */
-		BPF_MTAP(ifp, cur_tx->wb_mbuf);
-	}
-
-	/*
-	 * If there are no packets queued, bail.
-	 */
-	if (cur_tx == NULL)
-		return;
-
-	/*
-	 * Place the request for the upload interrupt
-	 * in the last descriptor in the chain. This way, if
-	 * we're chaining several packets at once, we'll only
-	 * get an interrupt once for the whole chain rather than
-	 * once for each packet.
-	 */
-	WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
-	cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
-	sc->wb_cdata.wb_tx_tail = cur_tx;
-
-	if (sc->wb_cdata.wb_tx_head == NULL) {
-		sc->wb_cdata.wb_tx_head = start_tx;
-		WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
-		CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
-	} else {
-		/*
-		 * We need to distinguish between the case where
-		 * the own bit is clear because the chip cleared it
-		 * and where the own bit is clear because we haven't
-		 * set it yet. The magic value WB_UNSET is just some
-		 * ramdomly chosen number which doesn't have the own
-	 	 * bit set. When we actually transmit the frame, the
-		 * status word will have _only_ the own bit set, so
-		 * the txeoc handler will be able to tell if it needs
-		 * to initiate another transmission to flush out pending
-		 * frames.
-		 */
-		WB_TXOWN(start_tx) = WB_UNSENT;
-	}
-
-	/*
-	 * Set a timeout in case the chip goes out to lunch.
-	 */
-	ifp->if_timer = 5;
-
-	return;
-}
-
-static void
-wb_init(xsc)
-	void			*xsc;
-{
-	struct wb_softc		*sc = xsc;
-
-	WB_LOCK(sc);
-	wb_init_locked(sc);
-	WB_UNLOCK(sc);
-}
-
-static void
-wb_init_locked(sc)
-	struct wb_softc		*sc;
-{
-	struct ifnet		*ifp = sc->wb_ifp;
-	int			i;
-	struct mii_data		*mii;
-
-	WB_LOCK_ASSERT(sc);
-	mii = device_get_softc(sc->wb_miibus);
-
-	/*
-	 * Cancel pending I/O and free all RX/TX buffers.
-	 */
-	wb_stop(sc);
-	wb_reset(sc);
-
-	sc->wb_txthresh = WB_TXTHRESH_INIT;
-
-	/*
-	 * Set cache alignment and burst length.
-	 */
-#ifdef foo
-	CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
-	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
-	WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
-#endif
-
-	CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
-	WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
-	switch(sc->wb_cachesize) {
-	case 32:
-		WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
-		break;
-	case 16:
-		WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
-		break;
-	case 8:
-		WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
-		break;
-	case 0:
-	default:
-		WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
-		break;
-	}
-
-	/* This doesn't tend to work too well at 100Mbps. */
-	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
-
-	/* Init our MAC address */
-	for (i = 0; i < ETHER_ADDR_LEN; i++) {
-		CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]);
-	}
-
-	/* Init circular RX list. */
-	if (wb_list_rx_init(sc) == ENOBUFS) {
-		device_printf(sc->wb_dev,
-		    "initialization failed: no memory for rx buffers\n");
-		wb_stop(sc);
-		return;
-	}
-
-	/* Init TX descriptors. */
-	wb_list_tx_init(sc);
-
-	/* If we want promiscuous mode, set the allframes bit. */
-	if (ifp->if_flags & IFF_PROMISC) {
-		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
-	} else {
-		WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
-	}
-
-	/*
-	 * Set capture broadcast bit to capture broadcast frames.
-	 */
-	if (ifp->if_flags & IFF_BROADCAST) {
-		WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
-	} else {
-		WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
-	}
-
-	/*
-	 * Program the multicast filter, if necessary.
-	 */
-	wb_setmulti(sc);
-
-	/*
-	 * Load the address of the RX list.
-	 */
-	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
-	CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
-
-	/*
-	 * Enable interrupts.
-	 */
-	CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
-	CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
-
-	/* Enable receiver and transmitter. */
-	WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
-	CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
-
-	WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
-	CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
-	WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
-
-	mii_mediachg(mii);
-
-	ifp->if_drv_flags |= IFF_DRV_RUNNING;
-	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
-
-	callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
-
-	return;
-}
-
-/*
- * Set media options.
- */
-static int
-wb_ifmedia_upd(ifp)
-	struct ifnet		*ifp;
-{
-	struct wb_softc		*sc;
-
-	sc = ifp->if_softc;
-
-	WB_LOCK(sc);
-	if (ifp->if_flags & IFF_UP)
-		wb_init_locked(sc);
-	WB_UNLOCK(sc);
-
-	return(0);
-}
-
-/*
- * Report current media status.
- */
-static void
-wb_ifmedia_sts(ifp, ifmr)
-	struct ifnet		*ifp;
-	struct ifmediareq	*ifmr;
-{
-	struct wb_softc		*sc;
-	struct mii_data		*mii;
-
-	sc = ifp->if_softc;
-
-	WB_LOCK(sc);
-	mii = device_get_softc(sc->wb_miibus);
-
-	mii_pollstat(mii);
-	ifmr->ifm_active = mii->mii_media_active;
-	ifmr->ifm_status = mii->mii_media_status;
-	WB_UNLOCK(sc);
-
-	return;
-}
-
-static int
-wb_ioctl(ifp, command, data)
-	struct ifnet		*ifp;
-	u_long			command;
-	caddr_t			data;
-{
-	struct wb_softc		*sc = ifp->if_softc;
-	struct mii_data		*mii;
-	struct ifreq		*ifr = (struct ifreq *) data;
-	int			error = 0;
-
-	switch(command) {
-	case SIOCSIFFLAGS:
-		WB_LOCK(sc);
-		if (ifp->if_flags & IFF_UP) {
-			wb_init_locked(sc);
-		} else {
-			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
-				wb_stop(sc);
-		}
-		WB_UNLOCK(sc);
-		error = 0;
-		break;
-	case SIOCADDMULTI:
-	case SIOCDELMULTI:
-		WB_LOCK(sc);
-		wb_setmulti(sc);
-		WB_UNLOCK(sc);
-		error = 0;
-		break;
-	case SIOCGIFMEDIA:
-	case SIOCSIFMEDIA:
-		mii = device_get_softc(sc->wb_miibus);
-		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
-		break;
-	default:
-		error = ether_ioctl(ifp, command, data);
-		break;
-	}
-
-	return(error);
-}
-
-static void
-wb_watchdog(ifp)
-	struct ifnet		*ifp;
-{
-	struct wb_softc		*sc;
-
-	sc = ifp->if_softc;
-
-	WB_LOCK(sc);
-	ifp->if_oerrors++;
-	if_printf(ifp, "watchdog timeout\n");
-#ifdef foo
-	if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
-		if_printf(ifp, "no carrier - transceiver cable problem?\n");
-#endif
-	wb_stop(sc);
-	wb_reset(sc);
-	wb_init_locked(sc);
-
-	if (ifp->if_snd.ifq_head != NULL)
-		wb_start_locked(ifp);
-	WB_UNLOCK(sc);
-
-	return;
-}
-
-/*
- * Stop the adapter and free any mbufs allocated to the
- * RX and TX lists.
- */
-static void
-wb_stop(sc)
-	struct wb_softc		*sc;
-{
-	register int		i;
-	struct ifnet		*ifp;
-
-	WB_LOCK_ASSERT(sc);
-	ifp = sc->wb_ifp;
-	ifp->if_timer = 0;
-
-	callout_stop(&sc->wb_stat_callout);
-
-	WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
-	CSR_WRITE_4(sc, WB_IMR, 0x00000000);
-	CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
-	CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
-
-	/*
-	 * Free data in the RX lists.
-	 */
-	for (i = 0; i < WB_RX_LIST_CNT; i++) {
-		if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
-			m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
-			sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
-		}
-	}
-	bzero((char *)&sc->wb_ldata->wb_rx_list,
-		sizeof(sc->wb_ldata->wb_rx_list));
-
-	/*
-	 * Free the TX list buffers.
-	 */
-	for (i = 0; i < WB_TX_LIST_CNT; i++) {
-		if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
-			m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
-			sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
-		}
-	}
-
-	bzero((char *)&sc->wb_ldata->wb_tx_list,
-		sizeof(sc->wb_ldata->wb_tx_list));
-
-	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
-
-	return;
-}
-
-/*
- * Stop all chip I/O so that the kernel's probe routines don't
- * get confused by errant DMAs when rebooting.
- */
-static void
-wb_shutdown(dev)
-	device_t		dev;
-{
-	struct wb_softc		*sc;
-
-	sc = device_get_softc(dev);
-
-	WB_LOCK(sc);
-	wb_stop(sc);
-	WB_UNLOCK(sc);
-
-	return;
-}
diff --git a/sys/pci/if_wbreg.h b/sys/pci/if_wbreg.h
deleted file mode 100644
index c5315c4..0000000
--- a/sys/pci/if_wbreg.h
+++ /dev/null
@@ -1,464 +0,0 @@
-/*-
- * Copyright (c) 1997, 1998
- *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Bill Paul.
- * 4. Neither the name of the author nor the names of any co-contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-/*
- * Winbond register definitions.
- */
-
-#define WB_BUSCTL		0x00	/* bus control */
-#define WB_TXSTART		0x04	/* tx start demand */
-#define WB_RXSTART		0x08	/* rx start demand */
-#define WB_RXADDR		0x0C	/* rx descriptor list start addr */
-#define WB_TXADDR		0x10	/* tx descriptor list start addr */
-#define WB_ISR			0x14	/* interrupt status register */
-#define WB_NETCFG		0x18	/* network config register */
-#define WB_IMR			0x1C	/* interrupt mask */
-#define WB_FRAMESDISCARDED	0x20	/* # of discarded frames */
-#define WB_SIO			0x24	/* MII and ROM/EEPROM access */
-#define WB_BOOTROMADDR		0x28
-#define WB_TIMER		0x2C	/* general timer */
-#define WB_CURRXCTL		0x30	/* current RX descriptor */
-#define WB_CURRXBUF		0x34	/* current RX buffer */
-#define WB_MAR0			0x38	/* multicast filter 0 */
-#define WB_MAR1			0x3C	/* multicast filter 1 */
-#define WB_NODE0		0x40	/* station address 0 */
-#define WB_NODE1		0x44	/* station address 1 */
-#define WB_BOOTROMSIZE		0x48	/* boot ROM size */
-#define WB_CURTXCTL		0x4C	/* current TX descriptor */
-#define WB_CURTXBUF		0x50	/* current TX buffer */
-
-/*
- * Bus control bits.
- */
-#define WB_BUSCTL_RESET		0x00000001
-#define WB_BUSCTL_ARBITRATION	0x00000002
-#define WB_BUSCTL_SKIPLEN	0x0000007C
-#define WB_BUSCTL_BUF_BIGENDIAN	0x00000080
-#define WB_BUSCTL_BURSTLEN	0x00003F00
-#define WB_BUSCTL_CACHEALIGN	0x0000C000
-#define WB_BUSCTL_DES_BIGENDIAN	0x00100000
-#define WB_BUSCTL_WAIT		0x00200000
-#define WB_BUSCTL_MUSTBEONE	0x00400000
-
-#define WB_SKIPLEN_1LONG	0x00000004
-#define WB_SKIPLEN_2LONG	0x00000008
-#define WB_SKIPLEN_3LONG	0x00000010
-#define WB_SKIPLEN_4LONG	0x00000020
-#define WB_SKIPLEN_5LONG	0x00000040
-
-#define WB_CACHEALIGN_NONE	0x00000000
-#define WB_CACHEALIGN_8LONG	0x00004000
-#define WB_CACHEALIGN_16LONG	0x00008000
-#define WB_CACHEALIGN_32LONG	0x0000C000
-
-#define WB_BURSTLEN_USECA	0x00000000
-#define WB_BURSTLEN_1LONG	0x00000100
-#define WB_BURSTLEN_2LONG	0x00000200
-#define WB_BURSTLEN_4LONG	0x00000400
-#define WB_BURSTLEN_8LONG	0x00000800
-#define WB_BURSTLEN_16LONG	0x00001000
-#define WB_BURSTLEN_32LONG	0x00002000
-
-#define WB_BUSCTL_CONFIG	(WB_CACHEALIGN_8LONG|WB_SKIPLEN_3LONG| \
-					WB_BURSTLEN_8LONG)
-
-/*
- * Interrupt status bits.
- */
-#define WB_ISR_TX_OK		0x00000001
-#define WB_ISR_TX_IDLE		0x00000002
-#define WB_ISR_TX_NOBUF		0x00000004
-#define WB_ISR_RX_EARLY		0x00000008
-#define WB_ISR_RX_ERR		0x00000010
-#define WB_ISR_TX_UNDERRUN	0x00000020
-#define WB_ISR_RX_OK		0x00000040
-#define WB_ISR_RX_NOBUF		0x00000080
-#define WB_ISR_RX_IDLE		0x00000100
-#define WB_ISR_TX_EARLY		0x00000400
-#define WB_ISR_TIMER_EXPIRED	0x00000800
-#define WB_ISR_BUS_ERR		0x00002000
-#define WB_ISR_ABNORMAL		0x00008000
-#define WB_ISR_NORMAL		0x00010000
-#define WB_ISR_RX_STATE		0x000E0000
-#define WB_ISR_TX_STATE		0x00700000
-#define WB_ISR_BUSERRTYPE	0x03800000
-
-/*
- * The RX_STATE and TX_STATE fields are not described anywhere in the
- * Winbond datasheet, however it appears that the Winbond chip is an
- * attempt at a DEC 'tulip' clone, hence the ISR register is identical
- * to that of the tulip chip and we can steal the bit definitions from
- * the tulip documentation.
- */
-#define WB_RXSTATE_STOPPED	0x00000000	/* 000 - Stopped */
-#define WB_RXSTATE_FETCH	0x00020000	/* 001 - Fetching descriptor */
-#define WB_RXSTATE_ENDCHECK	0x00040000	/* 010 - check for rx end */
-#define WB_RXSTATE_WAIT		0x00060000	/* 011 - waiting for packet */
-#define WB_RXSTATE_SUSPEND	0x00080000	/* 100 - suspend rx */
-#define WB_RXSTATE_CLOSE	0x000A0000	/* 101 - close tx desc */
-#define WB_RXSTATE_FLUSH	0x000C0000	/* 110 - flush from FIFO */
-#define WB_RXSTATE_DEQUEUE	0x000E0000	/* 111 - dequeue from FIFO */
-
-#define WB_TXSTATE_RESET	0x00000000	/* 000 - reset */
-#define WB_TXSTATE_FETCH	0x00100000	/* 001 - fetching descriptor */
-#define WB_TXSTATE_WAITEND	0x00200000	/* 010 - wait for tx end */
-#define WB_TXSTATE_READING	0x00300000	/* 011 - read and enqueue */
-#define WB_TXSTATE_RSVD		0x00400000	/* 100 - reserved */
-#define WB_TXSTATE_SETUP	0x00500000	/* 101 - setup packet */
-#define WB_TXSTATE_SUSPEND	0x00600000	/* 110 - suspend tx */
-#define WB_TXSTATE_CLOSE	0x00700000	/* 111 - close tx desc */
-
-/*
- * Network config bits.
- */
-#define WB_NETCFG_RX_ON		0x00000002
-#define WB_NETCFG_RX_ALLPHYS	0x00000008
-#define WB_NETCFG_RX_MULTI	0x00000010
-#define WB_NETCFG_RX_BROAD	0x00000020
-#define WB_NETCFG_RX_RUNT	0x00000040
-#define WB_NETCFG_RX_ERR	0x00000080
-#define WB_NETCFG_FULLDUPLEX	0x00000200
-#define WB_NETCFG_LOOPBACK	0x00000C00
-#define WB_NETCFG_TX_ON		0x00002000
-#define WB_NETCFG_TX_THRESH	0x001FC000
-#define WB_NETCFG_RX_EARLYTHRSH	0x1FE00000
-#define WB_NETCFG_100MBPS	0x20000000
-#define WB_NETCFG_TX_EARLY_ON	0x40000000
-#define WB_NETCFG_RX_EARLY_ON	0x80000000
-
-/*
- * The tx threshold can be adjusted in increments of 32 bytes.
- */
-#define WB_TXTHRESH(x)		((x >> 5) << 14)
-#define WB_TXTHRESH_CHUNK	32
-#define WB_TXTHRESH_INIT	0 /*72*/
- 
-/*
- * Interrupt mask bits.
- */
-#define WB_IMR_TX_OK		0x00000001
-#define WB_IMR_TX_IDLE		0x00000002
-#define WB_IMR_TX_NOBUF		0x00000004
-#define WB_IMR_RX_EARLY		0x00000008
-#define WB_IMR_RX_ERR		0x00000010
-#define WB_IMR_TX_UNDERRUN	0x00000020
-#define WB_IMR_RX_OK		0x00000040
-#define WB_IMR_RX_NOBUF		0x00000080
-#define WB_IMR_RX_IDLE		0x00000100
-#define WB_IMR_TX_EARLY		0x00000400
-#define WB_IMR_TIMER_EXPIRED	0x00000800
-#define WB_IMR_BUS_ERR		0x00002000
-#define WB_IMR_ABNORMAL		0x00008000
-#define WB_IMR_NORMAL		0x00010000
-
-#define WB_INTRS	\
-	(WB_IMR_RX_OK|WB_IMR_TX_OK|WB_IMR_RX_NOBUF|WB_IMR_RX_ERR|	\
-	WB_IMR_TX_NOBUF|WB_IMR_TX_UNDERRUN|WB_IMR_BUS_ERR|		\
-	WB_IMR_ABNORMAL|WB_IMR_NORMAL|WB_IMR_TX_EARLY)
-/*
- * Serial I/O (EEPROM/ROM) bits.
- */
-#define WB_SIO_EE_CS		0x00000001	/* EEPROM chip select */
-#define WB_SIO_EE_CLK		0x00000002	/* EEPROM clock */
-#define WB_SIO_EE_DATAIN	0x00000004	/* EEPROM data output */
-#define WB_SIO_EE_DATAOUT	0x00000008	/* EEPROM data input */
-#define WB_SIO_ROMDATA4		0x00000010
-#define WB_SIO_ROMDATA5		0x00000020
-#define WB_SIO_ROMDATA6		0x00000040
-#define WB_SIO_ROMDATA7		0x00000080
-#define WB_SIO_ROMCTL_WRITE	0x00000200
-#define WB_SIO_ROMCTL_READ	0x00000400
-#define WB_SIO_EESEL		0x00000800
-#define WB_SIO_MII_CLK		0x00010000	/* MDIO clock */
-#define WB_SIO_MII_DATAIN	0x00020000	/* MDIO data out */
-#define WB_SIO_MII_DIR		0x00040000	/* MDIO dir */
-#define WB_SIO_MII_DATAOUT	0x00080000	/* MDIO data in */
-
-#define WB_EECMD_WRITE		0x140
-#define WB_EECMD_READ		0x180
-#define WB_EECMD_ERASE		0x1c0
-
-/*
- * Winbond TX/RX descriptor structure.
- */
-
-struct wb_desc {
-	u_int32_t		wb_status;
-	u_int32_t		wb_ctl;
-	u_int32_t		wb_ptr1;
-	u_int32_t		wb_ptr2;
-};
-
-#define wb_data		wb_ptr1
-#define wb_next		wb_ptr2
-
-#define WB_RXSTAT_CRCERR	0x00000002
-#define WB_RXSTAT_DRIBBLE	0x00000004
-#define WB_RXSTAT_MIIERR	0x00000008
-#define WB_RXSTAT_LATEEVENT	0x00000040
-#define WB_RXSTAT_GIANT		0x00000080
-#define WB_RXSTAT_LASTFRAG	0x00000100
-#define WB_RXSTAT_FIRSTFRAG	0x00000200
-#define WB_RXSTAT_MULTICAST	0x00000400
-#define WB_RXSTAT_RUNT		0x00000800
-#define WB_RXSTAT_RXTYPE	0x00003000
-#define WB_RXSTAT_RXERR		0x00008000
-#define WB_RXSTAT_RXLEN		0x3FFF0000
-#define WB_RXSTAT_RXCMP		0x40000000
-#define WB_RXSTAT_OWN		0x80000000
-
-#define WB_RXBYTES(x)		((x & WB_RXSTAT_RXLEN) >> 16)
-#define WB_RXSTAT (WB_RXSTAT_FIRSTFRAG|WB_RXSTAT_LASTFRAG|WB_RXSTAT_OWN)
-
-#define WB_RXCTL_BUFLEN1	0x00000FFF
-#define WB_RXCTL_BUFLEN2	0x00FFF000
-#define WB_RXCTL_RLINK		0x01000000
-#define WB_RXCTL_RLAST		0x02000000
-
-#define WB_TXSTAT_DEFER		0x00000001
-#define WB_TXSTAT_UNDERRUN	0x00000002
-#define WB_TXSTAT_COLLCNT	0x00000078
-#define WB_TXSTAT_SQE		0x00000080
-#define WB_TXSTAT_ABORT		0x00000100
-#define WB_TXSTAT_LATECOLL	0x00000200
-#define WB_TXSTAT_NOCARRIER	0x00000400
-#define WB_TXSTAT_CARRLOST	0x00000800
-#define WB_TXSTAT_TXERR		0x00001000
-#define WB_TXSTAT_OWN		0x80000000
-
-#define WB_TXCTL_BUFLEN1	0x000007FF
-#define WB_TXCTL_BUFLEN2	0x003FF800
-#define WB_TXCTL_PAD		0x00800000
-#define WB_TXCTL_TLINK		0x01000000
-#define WB_TXCTL_TLAST		0x02000000
-#define WB_TXCTL_NOCRC		0x08000000
-#define WB_TXCTL_FIRSTFRAG	0x20000000
-#define WB_TXCTL_LASTFRAG	0x40000000
-#define WB_TXCTL_FINT		0x80000000
-
-#define WB_MAXFRAGS		16
-#define WB_RX_LIST_CNT		64
-#define WB_TX_LIST_CNT		128
-#define WB_MIN_FRAMELEN		60
-#define ETHER_ALIGN		2
-
-/*
- * A transmit 'super descriptor' is actually WB_MAXFRAGS regular
- * descriptors clumped together. The idea here is to emulate the
- * multi-fragment descriptor layout found in devices such as the
- * Texas Instruments ThunderLAN and 3Com boomerang and cylone chips.
- * The advantage to using this scheme is that it avoids buffer copies.
- * The disadvantage is that there's a certain amount of overhead due
- * to the fact that each 'fragment' is 16 bytes long. In my tests,
- * this limits top speed to about 10.5MB/sec. It should be more like
- * 11.5MB/sec. However, the upshot is that you can achieve better
- * results on slower machines: a Pentium 200 can pump out packets at
- * same speed as a PII 400.
- */
-struct wb_txdesc {
-	struct wb_desc		wb_frag[WB_MAXFRAGS];
-};
-
-#define WB_TXNEXT(x)	x->wb_ptr->wb_frag[x->wb_lastdesc].wb_next
-#define WB_TXSTATUS(x)	x->wb_ptr->wb_frag[x->wb_lastdesc].wb_status
-#define WB_TXCTL(x)	x->wb_ptr->wb_frag[x->wb_lastdesc].wb_ctl
-#define WB_TXDATA(x)	x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data
-
-#define WB_TXOWN(x)	x->wb_ptr->wb_frag[0].wb_status
-
-#define WB_UNSENT	0x1234
-
-#define WB_BUFBYTES	(1024 * sizeof(u_int32_t))
-
-struct wb_buf {
-	u_int32_t		wb_data[1024];
-};
-
-struct wb_list_data {
-	struct wb_buf		wb_rxbufs[WB_RX_LIST_CNT];
-	struct wb_desc		wb_rx_list[WB_RX_LIST_CNT];
-	struct wb_txdesc	wb_tx_list[WB_TX_LIST_CNT];
-};
-
-struct wb_chain {
-	struct wb_txdesc	*wb_ptr;
-	struct mbuf		*wb_mbuf;
-	struct wb_chain		*wb_nextdesc;
-	u_int8_t		wb_lastdesc;
-};
-
-struct wb_chain_onefrag {
-	struct wb_desc		*wb_ptr;
-	struct mbuf		*wb_mbuf;
-	void			*wb_buf;
-	struct wb_chain_onefrag	*wb_nextdesc;
-	u_int8_t		wb_rlast;
-};
-
-struct wb_chain_data {
-	u_int8_t		wb_pad[WB_MIN_FRAMELEN];
-	struct wb_chain_onefrag	wb_rx_chain[WB_RX_LIST_CNT];
-	struct wb_chain		wb_tx_chain[WB_TX_LIST_CNT];
-
-	struct wb_chain_onefrag	*wb_rx_head;
-
-	struct wb_chain		*wb_tx_head;
-	struct wb_chain		*wb_tx_tail;
-	struct wb_chain		*wb_tx_free;
-};
-
-struct wb_type {
-	u_int16_t		wb_vid;
-	u_int16_t		wb_did;
-	char			*wb_name;
-};
-
-struct wb_mii_frame {
-	u_int8_t		mii_stdelim;
-	u_int8_t		mii_opcode;
-	u_int8_t		mii_phyaddr;
-	u_int8_t		mii_regaddr;
-	u_int8_t		mii_turnaround;
-	u_int16_t		mii_data;
-};
-
-/*
- * MII constants
- */
-#define WB_MII_STARTDELIM	0x01
-#define WB_MII_READOP		0x02
-#define WB_MII_WRITEOP		0x01
-#define WB_MII_TURNAROUND	0x02
-
-struct wb_softc {
-	struct ifnet		*wb_ifp;	/* interface info */
-	device_t		wb_dev;
-	device_t		wb_miibus;
-	bus_space_handle_t	wb_bhandle;
-	bus_space_tag_t		wb_btag;
-	struct resource		*wb_res;
-	struct resource		*wb_irq;
-	void			*wb_intrhand;
-	struct wb_type		*wb_info;	/* Winbond adapter info */
-	u_int8_t		wb_type;
-	u_int16_t		wb_txthresh;
-	int			wb_cachesize;
-	caddr_t			wb_ldata_ptr;
-	struct wb_list_data	*wb_ldata;
-	struct wb_chain_data	wb_cdata;
-	struct callout		wb_stat_callout;
-	struct mtx		wb_mtx;
-};
-
-#define	WB_LOCK(_sc)		mtx_lock(&(_sc)->wb_mtx)
-#define	WB_UNLOCK(_sc)		mtx_unlock(&(_sc)->wb_mtx)
-#define	WB_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->wb_mtx, MA_OWNED)
-
-/*
- * register space access macros
- */
-#define CSR_WRITE_4(sc, reg, val)	\
-	bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
-#define CSR_WRITE_2(sc, reg, val)	\
-	bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
-#define CSR_WRITE_1(sc, reg, val)	\
-	bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
-
-#define CSR_READ_4(sc, reg)	\
-	bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg)
-#define CSR_READ_2(sc, reg)	\
-	bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg)
-#define CSR_READ_1(sc, reg)	\
-	bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg)
-
-#define WB_TIMEOUT		1000
-
-/*
- * General constants that are fun to know.
- *
- * Winbond PCI vendor ID
- */
-#define	WB_VENDORID		0x1050
-
-/*
- * Winbond device IDs.
- */
-#define	WB_DEVICEID_840F	0x0840
-
-/*
- * Compex vendor ID.
- */
-#define CP_VENDORID		0x11F6
-
-/*
- * Compex device IDs.
- */
-#define CP_DEVICEID_RL100	0x2011
-
-/*
- * PCI low memory base and low I/O base register, and
- * other PCI registers.
- */
-
-#define WB_PCI_VENDOR_ID	0x00
-#define WB_PCI_DEVICE_ID	0x02
-#define WB_PCI_COMMAND		0x04
-#define WB_PCI_STATUS		0x06
-#define WB_PCI_CLASSCODE	0x09
-#define WB_PCI_CACHELEN		0x0C
-#define WB_PCI_LATENCY_TIMER	0x0D
-#define WB_PCI_HEADER_TYPE	0x0E
-#define WB_PCI_LOIO		0x10
-#define WB_PCI_LOMEM		0x14
-#define WB_PCI_BIOSROM		0x30
-#define WB_PCI_INTLINE		0x3C
-#define WB_PCI_INTPIN		0x3D
-#define WB_PCI_MINGNT		0x3E
-#define WB_PCI_MINLAT		0x0F
-#define WB_PCI_RESETOPT		0x48
-#define WB_PCI_EEPROM_DATA	0x4C
-
-/* power management registers */
-#define WB_PCI_CAPID		0xDC /* 8 bits */
-#define WB_PCI_NEXTPTR		0xDD /* 8 bits */
-#define WB_PCI_PWRMGMTCAP	0xDE /* 16 bits */
-#define WB_PCI_PWRMGMTCTRL	0xE0 /* 16 bits */
-
-#define WB_PSTATE_MASK		0x0003
-#define WB_PSTATE_D0		0x0000
-#define WB_PSTATE_D1		0x0002
-#define WB_PSTATE_D2		0x0002
-#define WB_PSTATE_D3		0x0003
-#define WB_PME_EN		0x0010
-#define WB_PME_STATUS		0x8000