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| author | wpaul <wpaul@FreeBSD.org> | 2001-08-23 18:22:55 +0000 |
|---|---|---|
| committer | wpaul <wpaul@FreeBSD.org> | 2001-08-23 18:22:55 +0000 |
| commit | 0e50207f125544764aaeac812af46880ac4b2e8a (patch) | |
| tree | ae4bacec8ec8d05f0a304c5d3385ed31d6dd16c3 /sys/pci | |
| parent | 6e290545e10033972d1b507051ff8c36224baa45 (diff) | |
| download | FreeBSD-src-0e50207f125544764aaeac812af46880ac4b2e8a.zip FreeBSD-src-0e50207f125544764aaeac812af46880ac4b2e8a.tar.gz | |
Fix a bug in the ste_setmulti() routine. The NIC has 4 16-bit multicast
hash registers, not 2 32-bit ones. This would prevent the multicasr filter
from being programmed correctly in some cases.
Diffstat (limited to 'sys/pci')
| -rw-r--r-- | sys/pci/if_ste.c | 12 | ||||
| -rw-r--r-- | sys/pci/if_stereg.h | 4 |
2 files changed, 11 insertions, 5 deletions
diff --git a/sys/pci/if_ste.c b/sys/pci/if_ste.c index 2458c44..b68ccdd 100644 --- a/sys/pci/if_ste.c +++ b/sys/pci/if_ste.c @@ -583,8 +583,10 @@ static void ste_setmulti(sc) } /* first, zot all the existing hash bits */ - CSR_WRITE_4(sc, STE_MAR0, 0); - CSR_WRITE_4(sc, STE_MAR1, 0); + CSR_WRITE_2(sc, STE_MAR0, 0); + CSR_WRITE_2(sc, STE_MAR1, 0); + CSR_WRITE_2(sc, STE_MAR2, 0); + CSR_WRITE_2(sc, STE_MAR3, 0); /* now program new ones */ TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { @@ -597,8 +599,10 @@ static void ste_setmulti(sc) hashes[1] |= (1 << (h - 32)); } - CSR_WRITE_4(sc, STE_MAR0, hashes[0]); - CSR_WRITE_4(sc, STE_MAR1, hashes[1]); + CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); + CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); + CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); + CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); diff --git a/sys/pci/if_stereg.h b/sys/pci/if_stereg.h index 6081ec0..b369d6d 100644 --- a/sys/pci/if_stereg.h +++ b/sys/pci/if_stereg.h @@ -88,7 +88,9 @@ #define STE_TX_RECLAIM_THRESH 0x5D #define STE_PHYCTL 0x5E #define STE_MAR0 0x60 -#define STE_MAR1 0x64 +#define STE_MAR1 0x62 +#define STE_MAR2 0x64 +#define STE_MAR3 0x66 #define STE_STATS 0x68 #define STE_DMACTL_RXDMA_STOPPED 0x00000001 |
