- Update some comments regarding hardware details of the 8169 and

  note the existence of the 8169S and 8110S components. (The 8169
  is just a MAC, the 8169S and 8110S contain both a MAC and PHY.)

- Properly handle list and buffer addresses as 64-bit. The RX and
  TX DMA list addresses should be bus_addr_t's. Added RL_ADDR_HI()
  and RL_ADDR_LO() macros to obtain values for writing into chip
  registers.

- Set a slightly different TIMERINT value for 8169 NICs for improved
  performance.

- Change left out of previous commit log: added some additional
  hardware rev codes for other 10/100 chips and for the 8169S/8110S
  'rev C' gigE MACs.

1 files changed, 6 insertions, 3 deletions

diff --git a/sys/pci/if_rlreg.h b/sys/pci/if_rlreg.h
index 086b61b..4a32aef 100644
--- a/sys/pci/if_rlreg.h
+++ b/sys/pci/if_rlreg.h
@@ -593,6 +593,9 @@ struct rl_stats {
 				 RL_RDESC_STAT_FRAGLEN)
 #define RL_PKTSZ(x)		((x) >> 3)
 
+#define RL_ADDR_LO(y)	((u_int64_t) (y) & 0xFFFFFFFF)
+#define RL_ADDR_HI(y)	((u_int64_t) (y) >> 32)
+
 struct rl_softc;
 
 struct rl_dmaload_arg {
@@ -615,15 +618,15 @@ struct rl_list_data {
 	bus_dma_tag_t		rl_stag;	/* stats mapping tag */
 	bus_dmamap_t		rl_smap;	/* stats map */
 	struct rl_stats		*rl_stats;
-	u_int32_t		rl_stats_addr;
+	bus_addr_t		rl_stats_addr;
 	bus_dma_tag_t		rl_rx_list_tag;
 	bus_dmamap_t		rl_rx_list_map;
 	struct rl_desc		*rl_rx_list;
-	u_int32_t		rl_rx_list_addr;
+	bus_addr_t		rl_rx_list_addr;
 	bus_dma_tag_t		rl_tx_list_tag;
 	bus_dmamap_t		rl_tx_list_map;
 	struct rl_desc		*rl_tx_list;
-	u_int32_t		rl_tx_list_addr;
+	bus_addr_t		rl_tx_list_addr;
 };
 
 struct rl_softc {