diff options
| author | imp <imp@FreeBSD.org> | 2001-08-01 19:41:56 +0000 |
|---|---|---|
| committer | imp <imp@FreeBSD.org> | 2001-08-01 19:41:56 +0000 |
| commit | 15c0c44955c2d18e4582a561777c0536482d5478 (patch) | |
| tree | 13cf87427c226ea014ca373b7c76eea30d1a6252 /sys/pccard/i82365.h | |
| parent | 19b910842dfd92ac9592f6c8681e8d1d0f199805 (diff) | |
| download | FreeBSD-src-15c0c44955c2d18e4582a561777c0536482d5478.zip FreeBSD-src-15c0c44955c2d18e4582a561777c0536482d5478.tar.gz | |
TI cardbus bridges, 12xx and newer, have an interesting register. It
is the diagnostics register at offset 0x93. When bit 5 is set in this
register, bits 4-7 in ExCA register 0x5 being 0000 are required for
pci interrupt routing. When it is clear, then bit 4 of ExCA register
0x3 is used to enable it.
The only other issue is that when you route interrupts this way, you
must read ExCA register 0x4 in order to clear the interrupt, else you
get an interrupt storm.
Deal with this requirement by setting things up. It is believed that
this won't hurt other chipsets, but other chipsets may require their
own work arounds.
Diffstat (limited to 'sys/pccard/i82365.h')
| -rw-r--r-- | sys/pccard/i82365.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/sys/pccard/i82365.h b/sys/pccard/i82365.h index 633923f..41afe8c 100644 --- a/sys/pccard/i82365.h +++ b/sys/pccard/i82365.h @@ -138,7 +138,7 @@ #define PCIC_IOCARD 0x20 #define PCIC_MEMCARD 0x00 #define PCIC_CARDRESET 0x40 /* Card reset 0 = Reset, 1 = Normal */ -#define PCIC_INTR_ENA 0x10 /* Interrupt enable */ +#define PCIC_INTR_ENA 0x10 /* PCI CSC Interrupt enable */ /* For the Card Status Change register (PCIC_STAT_CHG) */ #define PCIC_CDTCH 0x08 /* Card Detect Change */ @@ -146,6 +146,14 @@ #define PCIC_BATWRN 0x02 /* Battery Warning */ #define PCIC_BATDED 0x01 /* Battery Dead */ +/* For the Card status change interrupt PCIC_STAT_INT */ +#define PCIC_CSCSELECT 0xf0 /* CSCSELECT */ +#define PCIC_SI_IRQ_SHIFT 4 +#define PCIC_CDEN 0x8 +#define PCIC_READYEN 0x4 +#define PCIC_BATWARNEN 0x2 +#define PCIC_BATDEADEN 0x1 + /* * For the Address Window Enable Register (PCIC_ADDRWINE) * The lower 6 bits contain enable bits for the memory |
