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| author | adrian <adrian@FreeBSD.org> | 2015-10-22 08:02:27 +0000 |
|---|---|---|
| committer | adrian <adrian@FreeBSD.org> | 2015-10-22 08:02:27 +0000 |
| commit | 05283b18cc3c59c966c884e05c30c1462aab3a22 (patch) | |
| tree | 5552fb723b8491e70498d0fe434f70f88e3ce962 /sys/mips | |
| parent | e76b6b65c98cb07b80bf222c1d0b9751f8be8579 (diff) | |
| download | FreeBSD-src-05283b18cc3c59c966c884e05c30c1462aab3a22.zip FreeBSD-src-05283b18cc3c59c966c884e05c30c1462aab3a22.tar.gz | |
arge: use 1-byte TX and RX alignment for AR9330/AR9331.
This part seems to work bug-free with single byte TX/RX buffer alignment.
This drops the CPU requirement to bridge 100mbit iperf from 100% CPU
to ~ 50% CPU.
Tested:
* AP121 (AR9330) SoC, highly magic netbooted kernel + USB rootfs
due to 4mb flash, 16mb RAM; doing bridging between arge0 and arge1.
Notes:
* Yes, I likely can also turn this on for the AR934x SoC family now.
But since hardware design apparently follows similar branching
strategies to software design, I'll go and make sure all the AR934x's
that made it out into shipping products work before I flip it on.
Diffstat (limited to 'sys/mips')
| -rw-r--r-- | sys/mips/atheros/if_arge.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sys/mips/atheros/if_arge.c b/sys/mips/atheros/if_arge.c index e91f085..4bdac2a 100644 --- a/sys/mips/atheros/if_arge.c +++ b/sys/mips/atheros/if_arge.c @@ -653,6 +653,8 @@ arge_attach(device_t dev) * Hardware workarounds. */ switch (ar71xx_soc) { + case AR71XX_SOC_AR9330: + case AR71XX_SOC_AR9331: case AR71XX_SOC_QCA9556: case AR71XX_SOC_QCA9558: /* Arbitrary alignment */ |
