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author | adrian <adrian@FreeBSD.org> | 2015-12-22 15:59:41 +0000 |
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committer | adrian <adrian@FreeBSD.org> | 2015-12-22 15:59:41 +0000 |
commit | 8efe8f9a36139471176a34f09e06d42658069a60 (patch) | |
tree | f78c06acae481e7e25c25f66ab548ec94a849654 /sys/mips | |
parent | 2c0acd5738e9eef0e9c7094962c3ce2d8ba624a6 (diff) | |
download | FreeBSD-src-8efe8f9a36139471176a34f09e06d42658069a60.zip FreeBSD-src-8efe8f9a36139471176a34f09e06d42658069a60.tar.gz |
[mips] Add TLB pagemask probing code, and print out the allowable page sizes.
This is from Stacey's work on larger kernel stack sizes for MIPS. Thanks!
Submitted by: sson
Diffstat (limited to 'sys/mips')
-rw-r--r-- | sys/mips/include/cpuinfo.h | 1 | ||||
-rw-r--r-- | sys/mips/include/pte.h | 13 | ||||
-rw-r--r-- | sys/mips/mips/cpu.c | 33 |
3 files changed, 46 insertions, 1 deletions
diff --git a/sys/mips/include/cpuinfo.h b/sys/mips/include/cpuinfo.h index baf3039..deeb93b 100644 --- a/sys/mips/include/cpuinfo.h +++ b/sys/mips/include/cpuinfo.h @@ -54,6 +54,7 @@ struct mips_cpuinfo { u_int8_t cpu_rev; u_int8_t cpu_impl; u_int8_t tlb_type; + u_int32_t tlb_pgmask; u_int16_t tlb_nentries; u_int8_t icache_virtual; boolean_t cache_coherent_dma; diff --git a/sys/mips/include/pte.h b/sys/mips/include/pte.h index 2f2f995..4b628db 100644 --- a/sys/mips/include/pte.h +++ b/sys/mips/include/pte.h @@ -188,4 +188,17 @@ typedef pt_entry_t *pd_entry_t; #endif #endif /* LOCORE */ + +/* PageMask Register (CP0 Register 5, Select 0) Values */ +#define MIPS3_PGMASK_MASKX 0x00001800 +#define MIPS3_PGMASK_4K 0x00000000 +#define MIPS3_PGMASK_16K 0x00006000 +#define MIPS3_PGMASK_64K 0x0001e000 +#define MIPS3_PGMASK_256K 0x0007e000 +#define MIPS3_PGMASK_1M 0x001fe000 +#define MIPS3_PGMASK_4M 0x007fe000 +#define MIPS3_PGMASK_16M 0x01ffe000 +#define MIPS3_PGMASK_64M 0x07ffe000 +#define MIPS3_PGMASK_256M 0x1fffe000 + #endif /* !_MACHINE_PTE_H_ */ diff --git a/sys/mips/mips/cpu.c b/sys/mips/mips/cpu.c index f7c74b4..a2b16ce 100644 --- a/sys/mips/mips/cpu.c +++ b/sys/mips/mips/cpu.c @@ -190,6 +190,14 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo) cpuinfo->l1.dc_size = cpuinfo->l1.dc_linesize * cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_nways; + /* + * Probe PageMask register to see what sizes of pages are supported + * by writing all one's and then reading it back. + */ + mips_wr_pagemask(~0); + cpuinfo->tlb_pgmask = mips_rd_pagemask(); + mips_wr_pagemask(MIPS3_PGMASK_4K); + #ifndef CPU_CNMIPS /* L2 cache */ if (!(cfg1 & MIPS_CONFIG_CM)) { @@ -289,8 +297,31 @@ cpu_identify(void) } else if (cpuinfo.tlb_type == MIPS_MMU_FIXED) { printf("Fixed mapping"); } - printf(", %d entries\n", cpuinfo.tlb_nentries); + printf(", %d entries ", cpuinfo.tlb_nentries); + } + + if (cpuinfo.tlb_pgmask) { + printf("("); + if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_MASKX) + printf("1K "); + printf("4K "); + if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_16K) + printf("16K "); + if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_64K) + printf("64K "); + if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_256K) + printf("256K "); + if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_1M) + printf("1M "); + if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_16M) + printf("16M "); + if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_64M) + printf("64M "); + if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_256M) + printf("256M "); + printf("pg sizes)"); } + printf("\n"); printf(" L1 i-cache: "); if (cpuinfo.l1.ic_linesize == 0) { |