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| author | adrian <adrian@FreeBSD.org> | 2015-12-24 04:37:19 +0000 |
|---|---|---|
| committer | adrian <adrian@FreeBSD.org> | 2015-12-24 04:37:19 +0000 |
| commit | 7f1fba1154060b21f6c2b13be3a730d04951ff16 (patch) | |
| tree | 3995a68cdd4de6433d68ccd8093146102536adc4 /sys/mips | |
| parent | a56b695591d54aeb8a2bfff084697f6e9493855c (diff) | |
| download | FreeBSD-src-7f1fba1154060b21f6c2b13be3a730d04951ff16.zip FreeBSD-src-7f1fba1154060b21f6c2b13be3a730d04951ff16.tar.gz | |
Add missing \n.
Otherwise you end up with:
Cache info:
picache_stride = 4096
picache_loopcount = 16
pdcache_stride = 4096
pdcache_loopcount = 8
cpu0: MIPS Technologies processor v80.150
MMU: Standard TLB, 32 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
L1 i-cache: 4 ways of 512 sets, 32 bytes per line
L1 d-cache: 4 ways of 256 sets, 32 bytes per line
L2 cache: disabled Config1=0xbee3519e<PerfCount,WatchRegs,MIPS16,EJTAG>
Config2=0x80000000
Config3=0x2420
Tested:
* MT7620 SoC
Diffstat (limited to 'sys/mips')
| -rw-r--r-- | sys/mips/mips/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sys/mips/mips/cpu.c b/sys/mips/mips/cpu.c index a2b16ce..5abd5b6 100644 --- a/sys/mips/mips/cpu.c +++ b/sys/mips/mips/cpu.c @@ -351,7 +351,7 @@ cpu_identify(void) printf(" L2 cache: "); if (cpuinfo.l2.dc_linesize == 0) { - printf("disabled"); + printf("disabled\n"); } else { printf("%d ways of %d sets, %d bytes per line, " "%d KiB total size\n", |
