MFC r258779,r258780,r258787,r258822:

Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit.  Instead use (1U << 31) which gets the
expected result.

Similar to the (1 << 31) case it is not defined to do (2 << 30).

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.

7 files changed, 33 insertions, 11 deletions

diff --git a/sys/mips/atheros/ar71xxreg.h b/sys/mips/atheros/ar71xxreg.h
index 5e3505b..f12c0df 100644
--- a/sys/mips/atheros/ar71xxreg.h
+++ b/sys/mips/atheros/ar71xxreg.h
@@ -162,7 +162,7 @@
 #define	AR71XX_BASE_FREQ		40000000
 #define	AR71XX_PLL_CPU_BASE		0x18050000
 #define	AR71XX_PLL_CPU_CONFIG		0x18050000
-#define		PLL_SW_UPDATE			(1 << 31)
+#define		PLL_SW_UPDATE			(1U << 31)
 #define		PLL_LOCKED			(1 << 30)
 #define		PLL_AHB_DIV_SHIFT		20
 #define		PLL_AHB_DIV_MASK		7
@@ -200,7 +200,7 @@
 #define	AR71XX_RST_BLOCK_BASE	0x18060000
 
 #define AR71XX_RST_WDOG_CONTROL	0x18060008
-#define		RST_WDOG_LAST			(1 << 31)
+#define		RST_WDOG_LAST			(1U << 31)
 #define		RST_WDOG_ACTION_MASK		3
 #define		RST_WDOG_ACTION_RESET		3
 #define		RST_WDOG_ACTION_NMI		2
@@ -303,7 +303,7 @@ typedef enum {
 #define AR71XX_MAC1_BASE	0x1A000000
 
 #define		AR71XX_MAC_CFG1			0x00
-#define			MAC_CFG1_SOFT_RESET		(1 << 31)
+#define			MAC_CFG1_SOFT_RESET		(1U << 31)
 #define			MAC_CFG1_SIMUL_RESET		(1 << 30)
 #define			MAC_CFG1_MAC_RX_BLOCK_RESET	(1 << 19)
 #define			MAC_CFG1_MAC_TX_BLOCK_RESET	(1 << 18)
@@ -332,7 +332,7 @@ typedef enum {
 #define		AR71XX_MAC_HDUPLEX		0x0C
 #define		AR71XX_MAC_MAX_FRAME_LEN	0x10
 #define		AR71XX_MAC_MII_CFG		0x20
-#define			MAC_MII_CFG_RESET		(1 << 31)
+#define			MAC_MII_CFG_RESET		(1U << 31)
 #define			MAC_MII_CFG_SCAN_AUTO_INC	(1 <<  5)
 #define			MAC_MII_CFG_PREAMBLE_SUP	(1 <<  4)
 #define			MAC_MII_CFG_CLOCK_SELECT_MASK	0x7
diff --git a/sys/mips/atheros/ar934xreg.h b/sys/mips/atheros/ar934xreg.h
index 2aa3f46..1df1cb2 100644
--- a/sys/mips/atheros/ar934xreg.h
+++ b/sys/mips/atheros/ar934xreg.h
@@ -103,16 +103,38 @@
 #define	AR934X_RESET_REG_BOOTSTRAP		(AR71XX_RST_BLOCK_BASE + 0xb0)
 #define	AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	(AR71XX_RST_BLOCK_BASE + 0xac)
 
+#define	AR934X_RESET_HOST		(1U << 31)
+#define	AR934X_RESET_SLIC		(1 << 30)
+#define	AR934X_RESET_HDMA		(1 << 29)
+#define	AR934X_RESET_EXTERNAL		(1 << 28)
+#define	AR934X_RESET_RTC		(1 << 27)
+#define	AR934X_RESET_PCIE_EP_INT	(1 << 26)
+#define	AR934X_RESET_CHKSUM_ACC		(1 << 25)
+#define	AR934X_RESET_FULL_CHIP		(1 << 24)
 #define	AR934X_RESET_GE1_MDIO		(1 << 23)
 #define	AR934X_RESET_GE0_MDIO		(1 << 22)
+#define	AR934X_RESET_CPU_NMI		(1 << 21)
+#define	AR934X_RESET_CPU_COLD		(1 << 20)
+#define	AR934X_RESET_HOST_RESET_INT	(1 << 19)
+#define	AR934X_RESET_PCIE_EP		(1 << 18)
+#define	AR934X_RESET_UART1		(1 << 17)
+#define	AR934X_RESET_DDR		(1 << 16)
+#define	AR934X_RESET_USB_PHY_PLL_PWD_EXT	(1 << 15)
+#define	AR934X_RESET_NANDF		(1 << 14)
 #define	AR934X_RESET_GE1_MAC		(1 << 13)
 #define	AR934X_RESET_ETH_SWITCH_ANALOG	(1 << 12)
 #define	AR934X_RESET_USB_PHY_ANALOG	(1 << 11)
+#define	AR934X_RESET_HOST_DMA_INT	(1 << 10)
 #define	AR934X_RESET_GE0_MAC		(1 << 9)
 #define	AR934X_RESET_ETH_SWITCH		(1 << 8)
+#define	AR934X_RESET_PCIE_PHY		(1 << 7)
+#define	AR934X_RESET_PCIE		(1 << 6)
 #define	AR934X_RESET_USB_HOST		(1 << 5)
 #define	AR934X_RESET_USB_PHY		(1 << 4)
 #define	AR934X_RESET_USBSUS_OVERRIDE	(1 << 3)
+#define	AR934X_RESET_LUT		(1 << 2)
+#define	AR934X_RESET_MBOX		(1 << 1)
+#define	AR934X_RESET_I2S		(1 << 0)
 
 #define	AR934X_BOOTSTRAP_SW_OPTION8	(1 << 23)
 #define	AR934X_BOOTSTRAP_SW_OPTION7	(1 << 22)
diff --git a/sys/mips/atheros/if_argevar.h b/sys/mips/atheros/if_argevar.h
index 9add674..cadd7ca 100644
--- a/sys/mips/atheros/if_argevar.h
+++ b/sys/mips/atheros/if_argevar.h
@@ -72,7 +72,7 @@
 #define ARGE_MDIO_READ(_sc, _reg)	\
 	ARGE_READ((_sc), (_reg))
 
-#define ARGE_DESC_EMPTY		(1 << 31)
+#define ARGE_DESC_EMPTY		(1U << 31)
 #define ARGE_DESC_MORE		(1 << 24)
 #define ARGE_DESC_SIZE_MASK	((1 << 12) - 1)
 #define	ARGE_DMASIZE(len)	((len) & ARGE_DESC_SIZE_MASK)
diff --git a/sys/mips/malta/gt_pci.c b/sys/mips/malta/gt_pci.c
index f9d8b83..3acc9b0 100644
--- a/sys/mips/malta/gt_pci.c
+++ b/sys/mips/malta/gt_pci.c
@@ -448,7 +448,7 @@ gt_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
 
 	/* Clear cause register bits. */
 	GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
-	GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1 << 31) | addr);
+	GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
 	/* 
 	 * Galileo system controller is special
 	 */
@@ -555,7 +555,7 @@ gt_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
 	/* Clear cause register bits. */
 	GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
 
-	GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1 << 31) | addr);
+	GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
 
 	/* 
 	 * Galileo system controller is special
diff --git a/sys/mips/nlm/dev/net/nae.c b/sys/mips/nlm/dev/net/nae.c
index 9f06372..b3790a2 100644
--- a/sys/mips/nlm/dev/net/nae.c
+++ b/sys/mips/nlm/dev/net/nae.c
@@ -1401,7 +1401,7 @@ nlm_nae_open_if(uint64_t nae_base, int nblock, int port_type,
 		mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
 		nlm_write_nae_reg(nae_base, conf1_reg,
 		    mac_cfg1	|
-		    (1 << 31)	|	/* soft reset */
+		    (1U << 31)	|	/* soft reset */
 		    (1 << 2)	|	/* rx enable */
 		    (1));		/* tx enable */
 
@@ -1415,7 +1415,7 @@ nlm_nae_open_if(uint64_t nae_base, int nblock, int port_type,
 
 		/* clear gmac reset */
 		mac_cfg1 = nlm_read_nae_reg(nae_base, conf1_reg);
-		nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 & ~(1 << 31));
+		nlm_write_nae_reg(nae_base, conf1_reg, mac_cfg1 & ~(1U << 31));
 
 		/* clear speed debug bit */
 		iface_ctrl3_reg = SGMII_NET_IFACE_CTRL3(nblock, iface);
diff --git a/sys/mips/nlm/xlp_machdep.c b/sys/mips/nlm/xlp_machdep.c
index f95592e..6a5dcb8 100644
--- a/sys/mips/nlm/xlp_machdep.c
+++ b/sys/mips/nlm/xlp_machdep.c
@@ -150,7 +150,7 @@ xlp_setup_mmu(void)
 
 	/* Enable no-read, no-exec, large-physical-address */
 	pagegrain = mips_rd_pagegrain();
-	pagegrain |= (1 << 31)	|	/* RIE */
+	pagegrain |= (1U << 31)	|	/* RIE */
 	    (1 << 30)		|	/* XIE */
 	    (1 << 29);			/* ELPA */
 	mips_wr_pagegrain(pagegrain);
diff --git a/sys/mips/rmi/pic.h b/sys/mips/rmi/pic.h
index 7b90eb9..d7e3add 100644
--- a/sys/mips/rmi/pic.h
+++ b/sys/mips/rmi/pic.h
@@ -214,7 +214,7 @@ void pic_setup_intr(int picintr, int irq, uint32_t cpumask, int level)
 
 	mtx_lock_spin(&xlr_pic_lock);
 	xlr_write_reg(mmio, PIC_IRT_0(picintr), cpumask);
-	xlr_write_reg(mmio, PIC_IRT_1(picintr), ((1 << 31) | (level << 30) |
+	xlr_write_reg(mmio, PIC_IRT_1(picintr), ((1U << 31) | (level << 30) |
 	    (1 << 6) | irq));
 	mtx_unlock_spin(&xlr_pic_lock);
 }