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| author | jchandra <jchandra@FreeBSD.org> | 2011-11-21 07:55:37 +0000 |
|---|---|---|
| committer | jchandra <jchandra@FreeBSD.org> | 2011-11-21 07:55:37 +0000 |
| commit | d6337b397f9c512423658207b3260c7470c9297a (patch) | |
| tree | 26063a4737d15e1c3a0c6baa7c2f70cdfc741fc1 /sys/mips | |
| parent | 82f1b9e8553535314355d6ec6308850e579d479b (diff) | |
| download | FreeBSD-src-d6337b397f9c512423658207b3260c7470c9297a.zip FreeBSD-src-d6337b397f9c512423658207b3260c7470c9297a.tar.gz | |
XLP processors have the release 2 pagegrain register
Add accessors to cpufunc.h
Obtained from: prabhath at netlogicmicro com
Diffstat (limited to 'sys/mips')
| -rw-r--r-- | sys/mips/include/cpufunc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sys/mips/include/cpufunc.h b/sys/mips/include/cpufunc.h index 02311cb..cd703ad 100644 --- a/sys/mips/include/cpufunc.h +++ b/sys/mips/include/cpufunc.h @@ -272,6 +272,9 @@ MIPS_RW32_COP0(status, MIPS_COP_0_STATUS); MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI); MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); #endif +#ifdef CPU_NLM +MIPS_RW32_COP0_SEL(pagegrain, MIPS_COP_0_TLB_PG_MASK, 1); +#endif #if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */ MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); |
