o) Add bus_teardown_intr for pci and ciu. This allows the Promise SATA

   driver to try to switch interrupt handlers at setup.  It's not a very
   good implementation of bus_teardown_intr, though.
o) Set cache line size and latency timers for PCI devices per Linux.

2 files changed, 27 insertions, 1 deletions

diff --git a/sys/mips/cavium/ciu.c b/sys/mips/cavium/ciu.c
index ee1dd4d..eb58928 100644
--- a/sys/mips/cavium/ciu.c
+++ b/sys/mips/cavium/ciu.c
@@ -78,6 +78,8 @@ static struct resource	*ciu_alloc_resource(device_t, device_t, int, int *,
 static int		ciu_setup_intr(device_t, device_t, struct resource *,
 				       int, driver_filter_t *, driver_intr_t *,
 				       void *, void **);
+static int		ciu_teardown_intr(device_t, device_t,
+					  struct resource *, void *);
 static void		ciu_hinted_child(device_t, const char *, int);
 
 static void		ciu_en0_intr_mask(void *);
@@ -230,6 +232,19 @@ ciu_setup_intr(device_t bus, device_t child, struct resource *res, int flags,
 	return (0);
 }
 
+static int
+ciu_teardown_intr(device_t bus, device_t child, struct resource *res,
+		  void *cookie)
+{
+	int error;
+
+	error = intr_event_remove_handler(cookie);
+	if (error != 0)
+		return (error);
+
+	return (0);
+}
+
 static void
 ciu_hinted_child(device_t bus, const char *dname, int dunit)
 {
@@ -342,7 +357,7 @@ static device_method_t ciu_methods[] = {
 	DEVMETHOD(bus_alloc_resource,	ciu_alloc_resource),
 	DEVMETHOD(bus_activate_resource,bus_generic_activate_resource),
 	DEVMETHOD(bus_setup_intr,	ciu_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+	DEVMETHOD(bus_teardown_intr,	ciu_teardown_intr),
 
 	DEVMETHOD(bus_add_child,	bus_generic_add_child),
 	DEVMETHOD(bus_hinted_child,	ciu_hinted_child),
diff --git a/sys/mips/cavium/octopci.c b/sys/mips/cavium/octopci.c
index af775a5..2b4188e 100644
--- a/sys/mips/cavium/octopci.c
+++ b/sys/mips/cavium/octopci.c
@@ -658,6 +658,16 @@ octopci_init_device(device_t dev, unsigned b, unsigned s, unsigned f, unsigned s
 	command |= PCIM_CMD_BUSMASTEREN;
 	octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1);
 
+	/* 
+	 * Set cache line size.  On Octeon it should be 128 bytes,
+	 * but according to Linux some Intel bridges have trouble
+	 * with values over 64 bytes, so use 64 bytes.
+	 */
+	octopci_write_config(dev, b, s, f, PCIR_CACHELNSZ, 16, 1);
+
+	/* Set latency timer.  */
+	octopci_write_config(dev, b, s, f, PCIR_LATTIMER, 48, 1);
+
 	/* Configure PCI-PCI bridges.  */
 	class = octopci_read_config(dev, b, s, f, PCIR_CLASS, 1);
 	if (class != PCIC_BRIDGE)
@@ -783,6 +793,7 @@ static device_method_t octopci_methods[] = {
 	DEVMETHOD(bus_activate_resource,octopci_activate_resource),
 	DEVMETHOD(bus_deactivate_resource,bus_generic_deactivate_resource),
 	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
 
 	DEVMETHOD(bus_add_child,	bus_generic_add_child),