Rather than shifting offsets by three, set register offset to 3. All our

bus interface does that's special here now is to use a 64-bit register size.
In theory, uart(4) ought to support a regsz as well as regshft and support
64-bit registers directly.

Also use the UART class's range rather than a hand-coded 1024 for the address
range.

3 files changed, 15 insertions, 16 deletions

diff --git a/sys/mips/cavium/uart_bus_octeonusart.c b/sys/mips/cavium/uart_bus_octeonusart.c
index c845ae7..f6855a7 100644
--- a/sys/mips/cavium/uart_bus_octeonusart.c
+++ b/sys/mips/cavium/uart_bus_octeonusart.c
@@ -105,11 +105,10 @@ uart_octeon_probe(device_t dev)
 	sc->sc_bas.bst = uart_bus_space_mem;
 	/*
 	 * XXX
-	 * RBR isn't really a great base address and it'd be great to not have
-	 * a hard-coded 1024.
+	 * RBR isn't really a great base address.
 	 */
-	if (bus_space_map(sc->sc_bas.bst, CVMX_MIO_UARTX_RBR(0), 1024,
-	    0, &sc->sc_bas.bsh) != 0)
+	if (bus_space_map(sc->sc_bas.bst, CVMX_MIO_UARTX_RBR(0),
+	    uart_getrange(sc->sc_class), 0, &sc->sc_bas.bsh) != 0)
 		return (ENXIO);
 	return (uart_bus_probe(dev, sc->sc_bas.regshft, 0, 0, unit));
 }
diff --git a/sys/mips/cavium/uart_cpu_octeonusart.c b/sys/mips/cavium/uart_cpu_octeonusart.c
index c03708e..e5d0e44 100644
--- a/sys/mips/cavium/uart_cpu_octeonusart.c
+++ b/sys/mips/cavium/uart_cpu_octeonusart.c
@@ -58,56 +58,56 @@ static uint8_t
 ou_bs_r_1(void *t, bus_space_handle_t handle, bus_size_t offset)
 {
 
-	return (oct_read64(handle + (offset << 3)));
+	return (oct_read64(handle + offset));
 }
 
 static uint16_t
 ou_bs_r_2(void *t, bus_space_handle_t handle, bus_size_t offset)
 {
 
-	return (oct_read64(handle + (offset << 3)));
+	return (oct_read64(handle + offset));
 }
 
 static uint32_t
 ou_bs_r_4(void *t, bus_space_handle_t handle, bus_size_t offset)
 {
 
-	return (oct_read64(handle + (offset << 3)));
+	return (oct_read64(handle + offset));
 }
 
 static uint64_t
 ou_bs_r_8(void *t, bus_space_handle_t handle, bus_size_t offset)
 {
 
-	return (oct_read64(handle + (offset << 3)));
+	return (oct_read64(handle + offset));
 }
 
 static void
 ou_bs_w_1(void *t, bus_space_handle_t bsh, bus_size_t offset, uint8_t value)
 {
 
-	oct_write64(bsh + (offset << 3), value);
+	oct_write64(bsh + offset, value);
 }
 
 static void
 ou_bs_w_2(void *t, bus_space_handle_t bsh, bus_size_t offset, uint16_t value)
 {
 
-	oct_write64(bsh + (offset << 3), value);
+	oct_write64(bsh + offset, value);
 }
 
 static void
 ou_bs_w_4(void *t, bus_space_handle_t bsh, bus_size_t offset, uint32_t value)
 {
 
-	oct_write64(bsh + (offset << 3), value);
+	oct_write64(bsh + offset, value);
 }
 
 static void
 ou_bs_w_8(void *t, bus_space_handle_t bsh, bus_size_t offset, uint64_t value)
 {
 
-	oct_write64(bsh + (offset << 3), value);
+	oct_write64(bsh + offset, value);
 }
 
 struct bus_space octeon_uart_tag = {
@@ -160,10 +160,10 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
 	di->ops = uart_getops(class);
 	di->bas.chan = 0;
 	/* XXX */
-	if (bus_space_map(di->bas.bst, CVMX_MIO_UARTX_RBR(0), 1024,
-	    0, &di->bas.bsh) != 0)
+	if (bus_space_map(di->bas.bst, CVMX_MIO_UARTX_RBR(0),
+	    uart_getrange(class), 0, &di->bas.bsh) != 0)
 		return (ENXIO);
-	di->bas.regshft = 0;
+	di->bas.regshft = 3;
 	di->bas.rclk = 0;
 	di->baudrate = 115200;
 	di->databits = 8;
diff --git a/sys/mips/cavium/uart_dev_oct16550.c b/sys/mips/cavium/uart_dev_oct16550.c
index b9bfe29..a7a54b3 100644
--- a/sys/mips/cavium/uart_dev_oct16550.c
+++ b/sys/mips/cavium/uart_dev_oct16550.c
@@ -420,7 +420,7 @@ struct uart_class uart_oct16550_class = {
 	oct16550_methods,
 	sizeof(struct oct16550_softc),
 	.uc_ops = &uart_oct16550_ops,
-	.uc_range = 8,
+	.uc_range = 8 << 3,
 	.uc_rclk = 0
 };