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| author | jchandra <jchandra@FreeBSD.org> | 2012-03-27 07:51:42 +0000 |
|---|---|---|
| committer | jchandra <jchandra@FreeBSD.org> | 2012-03-27 07:51:42 +0000 |
| commit | ee9de9d2f9900b9a02b2a4ef8485e218a09ab5f1 (patch) | |
| tree | db1870c26aeb31041edf7393054bbe2452d234fc /sys/mips | |
| parent | 5239156d843c7c11d7d3e55fbd44f249c9c52ea9 (diff) | |
| download | FreeBSD-src-ee9de9d2f9900b9a02b2a4ef8485e218a09ab5f1.zip FreeBSD-src-ee9de9d2f9900b9a02b2a4ef8485e218a09ab5f1.tar.gz | |
Update the L1D cache flush sequence when enabling threads.
Added more comments to the code.
Diffstat (limited to 'sys/mips')
| -rw-r--r-- | sys/mips/nlm/mpreset.S | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/sys/mips/nlm/mpreset.S b/sys/mips/nlm/mpreset.S index b35df63..cd05e75 100644 --- a/sys/mips/nlm/mpreset.S +++ b/sys/mips/nlm/mpreset.S @@ -55,24 +55,24 @@ .set noreorder li $8, LSU_DEBUG_DATA0 /* use register number to handle */ li $9, LSU_DEBUG_ADDR /* different ABIs */ - li t2, 0 - li t3, 0x200 + li t2, 0 /* index */ + li t3, 0x1000 /* loop count, 512 sets * 8 whatever? */ 1: sll v0, t2, 5 MTCR(0, 8) - ori v1, v0, 0x3 + ori v1, v0, 0x3 /* way0 | write_enable | write_active */ MTCR(3, 9) 2: MFCR(3, 9) - andi v1, 0x1 + andi v1, 0x1 /* wait for write_active == 0 */ bnez v1, 2b nop MTCR(0, 8) - ori v1, v0, 0x7 + ori v1, v0, 0x7 /* way1 | write_enable | write_active */ MTCR(3, 9) 3: MFCR(3, 9) - andi v1, 0x1 + andi v1, 0x1 /* wait for write_active == 0 */ bnez v1, 3b nop addi t2, 1 @@ -195,7 +195,7 @@ LEAF(xlp_enable_threads) mfc0 t1, MIPS_COP_0_STATUS move sp, t0 /* Restore the real SP */ - jr ra + jr.hb ra nop END(xlp_enable_threads) #endif |
