Further ar71xx MII support improvements.

* Flesh out the PLL configuration fetch function, which will return the PLL
  configuration based on the unit number and speed.
* Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config
  function - pass in a 'pll' value instead.
* Modify arge_set_pll() to:
  + fetch the PLL configuration
  + write the PLL configuration
  + update the MII speed configuration.

This will allow if_arge to override the PLL configuration as required.

Obtained from:	Linux/Atheros/OpenWRT

5 files changed, 61 insertions, 52 deletions

diff --git a/sys/mips/atheros/ar71xx_chip.c b/sys/mips/atheros/ar71xx_chip.c
index f83f703..0b083cc 100644
--- a/sys/mips/atheros/ar71xx_chip.c
+++ b/sys/mips/atheros/ar71xx_chip.c
@@ -222,25 +222,8 @@ ar71xx_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
 
 /* Speed is either 10, 100 or 1000 */
 static void
-ar71xx_chip_set_pll_ge(int unit, int speed)
+ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
 {
-	uint32_t pll;
-
-	switch (speed) {
-	case 10:
-		pll = PLL_ETH_INT_CLK_10;
-		break;
-	case 100:
-		pll = PLL_ETH_INT_CLK_100;
-		break;
-	case 1000:
-		pll = PLL_ETH_INT_CLK_1000;
-		break;
-	default:
-		printf("%s%d: invalid speed %d\n",
-		    __func__, unit, speed);
-		return;
-	}
 
 	switch (unit) {
 	case 0:
@@ -258,12 +241,6 @@ ar71xx_chip_set_pll_ge(int unit, int speed)
 		    __func__, unit);
 		return;
 	}
-
-	/*
-	 * AR71xx and AR913x require this; AR724x doesn't require
-	 * an MII clock change at all.
-	 */
-	ar71xx_chip_set_mii_speed(unit, speed);
 }
 
 static void
@@ -293,7 +270,24 @@ ar71xx_chip_ddr_flush_ip2(void)
 static uint32_t
 ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
 {
-	return 0;
+	uint32_t pll;
+
+	switch (speed) {
+	case 10:
+		pll = PLL_ETH_INT_CLK_10;
+		break;
+	case 100:
+		pll = PLL_ETH_INT_CLK_100;
+		break;
+	case 1000:
+		pll = PLL_ETH_INT_CLK_1000;
+		break;
+	default:
+		printf("%s%d: invalid speed %d\n", __func__, mac, speed);
+		pll = 0;
+	}
+
+	return (pll);
 }
 
 static void
diff --git a/sys/mips/atheros/ar71xx_cpudef.h b/sys/mips/atheros/ar71xx_cpudef.h
index 1fe2e09..c384d4c 100644
--- a/sys/mips/atheros/ar71xx_cpudef.h
+++ b/sys/mips/atheros/ar71xx_cpudef.h
@@ -35,7 +35,7 @@ struct ar71xx_cpu_def {
 	void (* ar71xx_chip_device_stop) (uint32_t);
 	void (* ar71xx_chip_device_start) (uint32_t);
 	int (* ar71xx_chip_device_stopped) (uint32_t);
-	void (* ar71xx_chip_set_pll_ge) (int, int);
+	void (* ar71xx_chip_set_pll_ge) (int, int, uint32_t);
 	void (* ar71xx_chip_set_mii_speed) (uint32_t, uint32_t);
 	void (* ar71xx_chip_set_mii_if) (uint32_t, ar71xx_mii_mode);
 	void (* ar71xx_chip_ddr_flush_ge) (int);
@@ -81,9 +81,9 @@ static inline int ar71xx_device_stopped(uint32_t mask)
 	return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask);
 }
 
-static inline void ar71xx_device_set_pll_ge(int unit, int speed)
+static inline void ar71xx_device_set_pll_ge(int unit, int speed, uint32_t pll)
 {
-	ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed);
+	ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed, pll);
 }
 
 static inline void ar71xx_device_set_mii_speed(int unit, int speed)
@@ -101,6 +101,11 @@ static inline void ar71xx_device_flush_ddr_ge(int unit)
 	ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge(unit);
 }
 
+static inline uint32_t ar71xx_device_get_eth_pll(unsigned int unit, int speed)
+{
+	return (ar71xx_cpu_ops->ar71xx_chip_get_eth_pll(unit, speed));
+}
+
 static inline void ar71xx_init_usb_peripheral(void)
 {
 	ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral();
diff --git a/sys/mips/atheros/ar724x_chip.c b/sys/mips/atheros/ar724x_chip.c
index d155297..4067ef8 100644
--- a/sys/mips/atheros/ar724x_chip.c
+++ b/sys/mips/atheros/ar724x_chip.c
@@ -139,7 +139,7 @@ ar724x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
  * AR7242 arge1.
  */
 static void
-ar724x_chip_set_pll_ge(int unit, int speed)
+ar724x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
 {
 
 	switch (unit) {
@@ -185,7 +185,7 @@ static uint32_t
 ar724x_chip_get_eth_pll(unsigned int mac, int speed)
 {
 
-	return 0;
+	return (0);
 }
 
 static void
diff --git a/sys/mips/atheros/ar91xx_chip.c b/sys/mips/atheros/ar91xx_chip.c
index d2fec2f..fa0e235 100644
--- a/sys/mips/atheros/ar91xx_chip.c
+++ b/sys/mips/atheros/ar91xx_chip.c
@@ -112,25 +112,9 @@ ar91xx_chip_device_stopped(uint32_t mask)
 }
 
 static void
-ar91xx_chip_set_pll_ge(int unit, int speed)
+ar91xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
 {
-	uint32_t pll;
 
-	switch(speed) {
-	case 10:
-		pll = AR91XX_PLL_VAL_10;
-		break;
-	case 100:
-		pll = AR91XX_PLL_VAL_100;
-		break;
-	case 1000:
-		pll = AR91XX_PLL_VAL_1000;
-		break;
-	default:
-		printf("%s%d: invalid speed %d\n",
-		    __func__, unit, speed);
-		return;
-	}
 	switch (unit) {
 	case 0:
 		ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
@@ -147,7 +131,6 @@ ar91xx_chip_set_pll_ge(int unit, int speed)
 		    __func__, unit);
 		return;
 	}
-	ar71xx_chip_set_mii_speed(unit, speed);
 }
 
 static void
@@ -179,8 +162,24 @@ ar91xx_chip_ddr_flush_ip2(void)
 static uint32_t
 ar91xx_chip_get_eth_pll(unsigned int mac, int speed)
 {
+	uint32_t pll;
+
+	switch(speed) {
+	case 10:
+		pll = AR91XX_PLL_VAL_10;
+		break;
+	case 100:
+		pll = AR91XX_PLL_VAL_100;
+		break;
+	case 1000:
+		pll = AR91XX_PLL_VAL_1000;
+		break;
+	default:
+		printf("%s%d: invalid speed %d\n", __func__, mac, speed);
+		pll = 0;
+	}
 
-	return 0;
+	return (pll);
 }
 
 static void
diff --git a/sys/mips/atheros/if_arge.c b/sys/mips/atheros/if_arge.c
index d52dcca..2c4a1be 100644
--- a/sys/mips/atheros/if_arge.c
+++ b/sys/mips/atheros/if_arge.c
@@ -776,10 +776,13 @@ arge_update_link_locked(struct arge_softc *sc)
 	if (mii->mii_media_status & IFM_ACTIVE) {
 
 		media = IFM_SUBTYPE(mii->mii_media_active);
-
 		if (media != IFM_NONE) {
 			sc->arge_link_status = 1;
 			duplex = mii->mii_media_active & IFM_GMASK;
+			ARGEDEBUG(sc, ARGE_DBG_MII, "%s: media=%d, duplex=%d\n",
+			    __func__,
+			    media,
+			    duplex);
 			arge_set_pll(sc, media, duplex);
 		}
 	} else {
@@ -791,7 +794,7 @@ static void
 arge_set_pll(struct arge_softc *sc, int media, int duplex)
 {
 	uint32_t		cfg, ifcontrol, rx_filtmask;
-	uint32_t		fifo_tx;
+	uint32_t		fifo_tx, pll;
 	int if_speed;
 
 	ARGEDEBUG(sc, ARGE_DBG_MII, "set_pll(%04x, %s)\n", media,
@@ -832,6 +835,8 @@ arge_set_pll(struct arge_softc *sc, int media, int duplex)
 		    "Unknown media %d\n", media);
 	}
 
+	ARGEDEBUG(sc, ARGE_DBG_MII, "%s: if_speed=%d\n", __func__, if_speed);
+
 	switch (ar71xx_soc) {
 		case AR71XX_SOC_AR7240:
 		case AR71XX_SOC_AR7241:
@@ -853,7 +858,13 @@ arge_set_pll(struct arge_softc *sc, int media, int duplex)
 	ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
 
 	/* set PLL registers */
-	ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed);
+	pll = ar71xx_device_get_eth_pll(sc->arge_mac_unit, if_speed);
+
+	/* XXX ensure pll != 0 */
+	ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll);
+
+	/* set MII registers */
+	ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed);
 }