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| author | neel <neel@FreeBSD.org> | 2010-03-04 05:23:08 +0000 |
|---|---|---|
| committer | neel <neel@FreeBSD.org> | 2010-03-04 05:23:08 +0000 |
| commit | 78a2d254338c4cf75acfe90af26bf1c53f7686f6 (patch) | |
| tree | 76f6e659fec1380f560085f6d1f80c9cf07c7c31 /sys/mips/sibyte | |
| parent | 2c774f7ff297aac0eba32bca605868fbebc0567c (diff) | |
| download | FreeBSD-src-78a2d254338c4cf75acfe90af26bf1c53f7686f6.zip FreeBSD-src-78a2d254338c4cf75acfe90af26bf1c53f7686f6.tar.gz | |
Add support for CPUs with cache coherent DMA. The two main changes are:
- We don't need to fall back to uncacheable memory to satisfy BUS_DMA_COHERENT
requests on these CPUs.
- The bus_dmamap_sync() is a no-op for these CPUs.
A side-effect of this change is rename DMAMAP_COHERENT flag to
DMAMAP_UNCACHEABLE. This conveys the purpose of the flag more accurately.
Reviewed by: gonzo, imp
Diffstat (limited to 'sys/mips/sibyte')
| -rw-r--r-- | sys/mips/sibyte/sb_machdep.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sys/mips/sibyte/sb_machdep.c b/sys/mips/sibyte/sb_machdep.c index c6043b8..8f59815 100644 --- a/sys/mips/sibyte/sb_machdep.c +++ b/sys/mips/sibyte/sb_machdep.c @@ -220,6 +220,13 @@ mips_init(void) mips_cpu_init(); /* + * Sibyte has a L1 data cache coherent with DMA. This includes + * on-chip network interfaces as well as PCI/HyperTransport bus + * masters. + */ + cpuinfo.cache_coherent_dma = TRUE; + + /* * XXX * The kernel is running in 32-bit mode but the CFE is running in * 64-bit mode. So the SR_KX bit in the status register is turned |
