As discussed on IRC and at BSDcan, move the mips32/* directories up a

level.  The distinction was artificial.  Some more movement around the
deck charis is likely depending on the fallout from this one.

Paths were corrected after the svn mv.  Hope that's OK.

10 files changed, 1116 insertions, 0 deletions

diff --git a/sys/mips/sentry5/files.sentry5 b/sys/mips/sentry5/files.sentry5
new file mode 100644
index 0000000..61038e0
--- /dev/null
+++ b/sys/mips/sentry5/files.sentry5
@@ -0,0 +1,14 @@
+# $FreeBSD$
+
+# TODO: Add attachment elsehwere in the tree
+# for USB 1.1 OHCI, Ethernet and IPSEC cores
+# which are believed to be devices we have drivers for
+# which just need to be tweaked for attachment to an SSB system bus.
+
+mips/sentry5/s5_machdep.c		standard
+dev/siba/siba.c					optional siba
+dev/siba/siba_pcib.c				optional siba pci
+mips/sentry5/siba_cc.c			optional siba
+
+# notyet
+#mips/sentry5/siba_mips.c			optional siba
diff --git a/sys/mips/sentry5/obio.c b/sys/mips/sentry5/obio.c
new file mode 100644
index 0000000..1c1b9c9
--- /dev/null
+++ b/sys/mips/sentry5/obio.c
@@ -0,0 +1,187 @@
+/*	$NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $	*/
+
+/*-
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * On-board device autoconfiguration support for Broadcom Sentry5
+ * based boards.
+ * XXX This is totally bogus and is just enough to get the console hopefully
+ * running on the sentry5.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/mips32/sentry5/obiovar.h>
+#include <mips/mips32/sentry5/sentry5reg.h>
+
+int	obio_probe(device_t);
+int	obio_attach(device_t);
+
+/*
+ * A bit tricky and hackish. Since we need OBIO to rely
+ * on PCI we make it pseudo-pci device. But there should 
+ * be only one such device, so we use this static flag 
+ * to prevent false positives on every realPCI device probe. 
+ */
+static int have_one = 0;
+
+int
+obio_probe(device_t dev)
+{
+	if(!have_one)
+	{
+		have_one = 1;
+		return 0;
+	}
+	else
+		return (ENXIO);
+}
+
+int
+obio_attach(device_t dev)
+{
+	struct obio_softc *sc = device_get_softc(dev);
+
+	sc->oba_st = MIPS_BUS_SPACE_IO;
+	sc->oba_addr = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
+	sc->oba_size = 0x03FFFFFF;	/* XXX sb pci bus 0 aperture size? */
+	sc->oba_rman.rm_type = RMAN_ARRAY;
+	sc->oba_rman.rm_descr = "OBIO I/O";
+	if (rman_init(&sc->oba_rman) != 0 ||
+	    rman_manage_region(&sc->oba_rman,
+	    sc->oba_addr, sc->oba_addr + sc->oba_size) != 0)
+		panic("obio_attach: failed to set up I/O rman");
+	sc->oba_irq_rman.rm_type = RMAN_ARRAY;
+	sc->oba_irq_rman.rm_descr = "OBIO IRQ";
+
+	/* 
+	 * This module is intended for UART purposes only and
+	 * it's IRQ is 4
+	 */
+	if (rman_init(&sc->oba_irq_rman) != 0 ||
+	    rman_manage_region(&sc->oba_irq_rman, 4, 4) != 0)
+		panic("obio_attach: failed to set up IRQ rman");
+
+	device_add_child(dev, "uart", 0);
+	bus_generic_probe(dev);
+	bus_generic_attach(dev);
+
+	return (0);
+}
+
+static struct resource *
+obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+    u_long start, u_long end, u_long count, u_int flags)
+{
+	struct resource *rv;
+	struct rman *rm;
+	bus_space_tag_t bt = 0;
+	bus_space_handle_t bh = 0;
+	struct obio_softc *sc = device_get_softc(bus);
+
+	switch (type) {
+	case SYS_RES_IRQ:
+		rm = &sc->oba_irq_rman;
+		break;
+	case SYS_RES_MEMORY:
+		return (NULL);
+	case SYS_RES_IOPORT:
+		rm = &sc->oba_rman;
+		bt = sc->oba_st;
+		bh = sc->oba_addr;
+		start = bh;
+		break;
+	default:
+		return (NULL);
+	}
+
+
+	rv = rman_reserve_resource(rm, start, end, count, flags, child);
+	if (rv == NULL) 
+		return (NULL);
+	if (type == SYS_RES_IRQ)
+		return (rv);
+	rman_set_rid(rv, *rid);
+	rman_set_bustag(rv, bt);
+	rman_set_bushandle(rv, bh);
+	
+	if (0) {
+		if (bus_activate_resource(child, type, *rid, rv)) {
+			rman_release_resource(rv);
+			return (NULL);
+		}
+	}
+	return (rv);
+
+}
+
+static int
+obio_activate_resource(device_t bus, device_t child, int type, int rid,
+    struct resource *r)
+{
+	return (0);
+}
+static device_method_t obio_methods[] = {
+	DEVMETHOD(device_probe, obio_probe),
+	DEVMETHOD(device_attach, obio_attach),
+
+	DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
+	DEVMETHOD(bus_activate_resource, obio_activate_resource),
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
+	{0, 0},
+};
+
+static driver_t obio_driver = {
+	"obio",
+	obio_methods,
+	sizeof(struct obio_softc),
+};
+static devclass_t obio_devclass;
+
+DRIVER_MODULE(obio, pci, obio_driver, obio_devclass, 0, 0);
diff --git a/sys/mips/sentry5/obiovar.h b/sys/mips/sentry5/obiovar.h
new file mode 100644
index 0000000..27c1b37
--- /dev/null
+++ b/sys/mips/sentry5/obiovar.h
@@ -0,0 +1,58 @@
+/*	$NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $	*/
+
+/*-
+ * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#ifndef _SENTRY5_OBIOVAR_H_
+#define	_SENTRY5_OBIOVAR_H_
+
+#include <sys/rman.h>
+
+struct obio_softc {
+	bus_space_tag_t oba_st;		/* bus space tag */
+	bus_addr_t oba_addr;		/* address of device */
+	bus_size_t oba_size;		/* size of device */
+	int oba_width;			/* bus width */
+	int oba_irq;			/* XINT interrupt bit # */
+	struct rman oba_rman;
+	struct rman oba_irq_rman;
+	
+};
+extern struct bus_space obio_bs_tag;
+
+#endif /* _SENTRY5_OBIOVAR_H_ */
diff --git a/sys/mips/sentry5/s5_machdep.c b/sys/mips/sentry5/s5_machdep.c
new file mode 100644
index 0000000..c8a2bae
--- /dev/null
+++ b/sys/mips/sentry5/s5_machdep.c
@@ -0,0 +1,241 @@
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <machine/cpuregs.h>
+
+#include <mips/mips32/sentry5/s5reg.h>
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/user.h>
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+#include <vm/vm_pager.h>
+
+#include <machine/cache.h>
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuinfo.h>
+#include <machine/cpufunc.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/intr_machdep.h>
+#include <machine/locore.h>
+#include <machine/md_var.h>
+#include <machine/pte.h>
+#include <machine/sigframe.h>
+#include <machine/tlb.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#ifdef CFE
+#include <dev/cfe/cfe_api.h>
+#endif
+
+#ifdef CFE
+extern uint32_t cfe_handle;
+extern uint32_t cfe_vector;
+#endif
+
+extern int *edata;
+extern int *end;
+
+static void
+mips_init(void)
+{
+	int i;
+
+	printf("entry: mips_init()\n");
+
+#ifdef CFE
+	/*
+	 * Query DRAM memory map from CFE.
+	 */
+	physmem = 0;
+	for (i = 0; i < 10; i += 2) {
+		int result;
+		uint64_t addr, len, type;
+
+		result = cfe_enummem(i, 0, &addr, &len, &type);
+		if (result < 0) {
+			phys_avail[i] = phys_avail[i + 1] = 0;
+			break;
+		}
+		if (type != CFE_MI_AVAILABLE)
+			continue;
+
+		phys_avail[i] = addr;
+		if (i == 0 && addr == 0) {
+			/*
+			 * If this is the first physical memory segment probed
+			 * from CFE, omit the region at the start of physical
+			 * memory where the kernel has been loaded.
+			 */
+			phys_avail[i] += MIPS_KSEG0_TO_PHYS((vm_offset_t)&end);
+		}
+		phys_avail[i + 1] = addr + len;
+		physmem += len;
+	}
+
+	realmem = btoc(physmem);
+#endif
+
+	physmem = realmem;
+
+	init_param1();
+	init_param2(physmem);
+	mips_cpu_init();
+	pmap_bootstrap();
+	mips_proc0_init();
+	mutex_init();
+#ifdef DDB
+	kdb_init();
+#endif
+}
+
+void
+platform_halt(void)
+{
+
+}
+
+
+void
+platform_identify(void)
+{
+
+}
+
+void
+platform_reset(void)
+{
+
+#if defined(CFE)
+	cfe_exit(0, 0);
+#else
+	*((volatile uint8_t *)MIPS_PHYS_TO_KSEG1(SENTRY5_EXTIFADR)) = 0x80;
+#endif
+}
+
+void
+platform_trap_enter(void)
+{
+
+}
+
+void
+platform_trap_exit(void)
+{
+
+}
+
+void
+platform_start(__register_t a0 __unused, __register_t a1 __unused, 
+    __register_t a2 __unused, __register_t a3 __unused)
+{
+	vm_offset_t kernend;
+	uint64_t platform_counter_freq;
+
+	/* clear the BSS and SBSS segments */
+	kernend = round_page((vm_offset_t)&end);
+	memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+
+#ifdef CFE
+	/*
+	 * Initialize CFE firmware trampolines before
+	 * we initialize the low-level console.
+	 */
+	if (cfe_handle != 0)
+		cfe_init(cfe_handle, cfe_vector);
+#endif
+	cninit();
+
+#ifdef CFE
+	if (cfe_handle == 0)
+		panic("CFE was not detected by locore.\n");
+#endif
+	mips_init();
+
+# if 0
+	/*
+	 * Probe the Broadcom Sentry5's on-chip PLL clock registers
+	 * and discover the CPU pipeline clock and bus clock
+	 * multipliers from this.
+	 * XXX: Wrong place. You have to ask the ChipCommon
+	 * or External Interface cores on the SiBa.
+	 */
+	uint32_t busmult, cpumult, refclock, clkcfg1;
+#define S5_CLKCFG1_REFCLOCK_MASK	0x0000001F
+#define S5_CLKCFG1_BUSMULT_MASK		0x000003E0
+#define S5_CLKCFG1_BUSMULT_SHIFT	5
+#define S5_CLKCFG1_CPUMULT_MASK		0xFFFFFC00
+#define S5_CLKCFG1_CPUMULT_SHIFT	10
+
+	counter_freq = 100000000;	/* XXX */
+
+	clkcfg1 = s5_rd_clkcfg1();
+	printf("clkcfg1 = 0x%08x\n", clkcfg1);
+
+	refclock = clkcfg1 & 0x1F;
+	busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1;
+	cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1;
+
+	printf("refclock = %u\n", refclock);
+	printf("busmult = %u\n", busmult);
+	printf("cpumult = %u\n", cpumult);
+
+	counter_freq = cpumult * refclock;
+# else
+	platform_counter_freq = 200 * 1000 * 1000; /* Sentry5 is 200MHz */
+# endif
+
+	mips_timer_init_params(platform_counter_freq, 0);
+}
diff --git a/sys/mips/sentry5/s5reg.h b/sys/mips/sentry5/s5reg.h
new file mode 100644
index 0000000..71643d0
--- /dev/null
+++ b/sys/mips/sentry5/s5reg.h
@@ -0,0 +1,58 @@
+/* $FreeBSD$ */
+
+#ifndef _MIPS32_SENTRY5_SENTRY5REG_H_
+#define _MIPS32_SENTRY5_SENTRY5REG_H_
+
+#define	SENTRY5_UART0ADR	0x18000300
+#define	SENTRY5_UART1ADR	0x18000400
+
+/* Reset register implemented here in a PLD device. */
+#define	SENTRY5_EXTIFADR	0x1F000000
+#define	SENTRY5_DORESET		0x80
+
+/*
+ * Custom CP0 register macros.
+ * XXX: This really needs the mips cpuregs.h file for the barrier.
+ */
+#define S5_RDRW32_C0P0_CUST22(n,r)				\
+static __inline u_int32_t					\
+s5_rd_ ## n (void)						\
+{								\
+	int v0;							\
+	__asm __volatile ("mfc0 %[v0], $22, "__XSTRING(r)" ;"	\
+			  : [v0] "=&r"(v0));			\
+	/*mips_barrier();*/					\
+	return (v0);						\
+}								\
+static __inline void						\
+s5_wr_ ## n (u_int32_t a0)					\
+{								\
+	__asm __volatile ("mtc0 %[a0], $22, "__XSTRING(r)" ;"	\
+			 __XSTRING(COP0_SYNC)";"		\
+			 "nop;"					\
+			 "nop;"					\
+			 :					\
+			 : [a0] "r"(a0));			\
+	/*mips_barrier();*/					\
+} struct __hack
+
+/*
+ * All 5 of these sub-registers are used by Linux.
+ * There is a further custom register at 25 which is not used.
+ */
+#define	S5_CP0_DIAG	0
+#define	S5_CP0_CLKCFG1	1
+#define	S5_CP0_CLKCFG2	2
+#define	S5_CP0_SYNC	3
+#define	S5_CP0_CLKCFG3	4
+#define	S5_CP0_RESET	5
+
+/* s5_[rd|wr]_xxx() */
+S5_RDRW32_C0P0_CUST22(diag, S5_CP0_DIAG);
+S5_RDRW32_C0P0_CUST22(clkcfg1, S5_CP0_CLKCFG1);
+S5_RDRW32_C0P0_CUST22(clkcfg2, S5_CP0_CLKCFG2);
+S5_RDRW32_C0P0_CUST22(sync, S5_CP0_SYNC);
+S5_RDRW32_C0P0_CUST22(clkcfg3, S5_CP0_CLKCFG3);
+S5_RDRW32_C0P0_CUST22(reset, S5_CP0_RESET);
+
+#endif /* _MIPS32_SENTRY5_SENTRY5REG_H_ */
diff --git a/sys/mips/sentry5/siba_cc.c b/sys/mips/sentry5/siba_cc.c
new file mode 100644
index 0000000..cd78f0b
--- /dev/null
+++ b/sys/mips/sentry5/siba_cc.c
@@ -0,0 +1,154 @@
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Child driver for ChipCommon core.
+ * This is not MI code at the moment.
+ * Two 16C550 compatible UARTs live here. On the WGT634U, uart1 is the
+ * system console, and uart0 is not pinned out.
+ *  Because their presence is conditional, they should probably
+ *  be attached from here.
+ * GPIO lives here.
+ * The hardware watchdog lives here.
+ * Clock control registers live here.
+ *  You don't need to read them to determine the clock speed on the 5365,
+ *  which is always 200MHz and thus may be hardcoded (for now).
+ * Flash config registers live here. There may or may not be system flash.
+ * The external interface bus lives here (conditionally).
+ * There is a JTAG interface here which may be used to attach probes to
+ * the SoC for debugging.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <dev/siba/sibavar.h>
+#include <dev/siba/sibareg.h>
+#include <dev/siba/siba_ids.h>
+
+static int	siba_cc_attach(device_t);
+static int	siba_cc_probe(device_t);
+static void	siba_cc_intr(void *v);
+
+static int
+siba_cc_probe(device_t dev)
+{
+
+	if (siba_get_vendor(dev) == SIBA_VID_BROADCOM &&
+	    siba_get_device(dev) == SIBA_DEVID_CHIPCOMMON) {
+		device_set_desc(dev, "ChipCommon core");
+		return (BUS_PROBE_DEFAULT);
+	}
+
+	return (ENXIO);
+}
+
+struct siba_cc_softc {
+	void *notused;
+};
+
+static int
+siba_cc_attach(device_t dev)
+{
+	//struct siba_cc_softc *sc = device_get_softc(dev);
+	struct resource *mem;
+	struct resource *irq;
+	int rid;
+
+	/*
+	 * Allocate the resources which the parent bus has already
+	 * determined for us.
+	 * TODO: interrupt routing
+	 */
+#define MIPS_MEM_RID 0x20
+	rid = MIPS_MEM_RID;
+	mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+	if (mem == NULL) {
+		device_printf(dev, "unable to allocate memory\n");
+		return (ENXIO);
+	}
+
+	rid = 0;
+	irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
+	if (irq == NULL) {
+		device_printf(dev, "unable to allocate irq\n");
+		return (ENXIO);
+	}
+
+	/* now setup the interrupt */
+	/* may be fast, exclusive or mpsafe at a later date */
+
+	/*
+	 * XXX is this interrupt line in ChipCommon used for anything
+	 * other than the uart? in that case we shouldn't hog it ourselves
+	 * and let uart claim it to avoid polled mode.
+	 */
+	int err;
+	void *cookie;
+	err = bus_setup_intr(dev, irq, INTR_TYPE_TTY, NULL, siba_cc_intr, NULL,
+	    &cookie);
+	if (err != 0) {
+		device_printf(dev, "unable to setup intr\n");
+		return (ENXIO);
+	}
+
+	/* TODO: attach uart child */
+
+	return (0);
+}
+
+static void
+siba_cc_intr(void *v)
+{
+
+}
+
+static device_method_t siba_cc_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_attach,	siba_cc_attach),
+	DEVMETHOD(device_probe,		siba_cc_probe),
+
+	{0, 0},
+};
+
+static driver_t siba_cc_driver = {
+	"siba_cc",
+	siba_cc_methods,
+	sizeof(struct siba_softc),
+};
+static devclass_t siba_cc_devclass;
+
+DRIVER_MODULE(siba_cc, siba, siba_cc_driver, siba_cc_devclass, 0, 0);
diff --git a/sys/mips/sentry5/siba_mips.c b/sys/mips/sentry5/siba_mips.c
new file mode 100644
index 0000000..676da83
--- /dev/null
+++ b/sys/mips/sentry5/siba_mips.c
@@ -0,0 +1,113 @@
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Child driver for MIPS 3302 core.
+ * Interrupt controller registers live here. Interrupts may not be routed
+ * to the MIPS core if they are masked out.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <dev/siba/sibavar.h>
+#include <dev/siba/sibareg.h>
+#include <dev/siba/siba_ids.h>
+
+static int	siba_mips_attach(device_t);
+static int	siba_mips_probe(device_t);
+
+static int
+siba_mips_probe(device_t dev)
+{
+
+	if (siba_get_vendor(dev) == SIBA_VID_BROADCOM &&
+	    siba_get_device(dev) == SIBA_DEVID_MIPS_3302) {
+		device_set_desc(dev, "MIPS 3302 processor");
+		return (BUS_PROBE_DEFAULT);
+	}
+
+	return (ENXIO);
+}
+
+struct siba_mips_softc {
+	void *notused;
+};
+
+static int
+siba_mips_attach(device_t dev)
+{
+	//struct siba_mips_softc *sc = device_get_softc(dev);
+	struct resource *mem;
+	int rid;
+
+	/*
+	 * Allocate the resources which the parent bus has already
+	 * determined for us.
+	 * TODO: interrupt routing
+	 */
+#define MIPS_MEM_RID 0x20
+	rid = MIPS_MEM_RID;
+	mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+	    RF_ACTIVE);
+	if (mem == NULL) {
+		device_printf(dev, "unable to allocate memory\n");
+		return (ENXIO);
+	}
+#if 0
+	device_printf(dev, "start %08lx size %04lx\n",
+	    rman_get_start(mem), rman_get_size(mem));
+#endif
+
+	return (0);
+}
+
+static device_method_t siba_mips_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_attach,	siba_mips_attach),
+	DEVMETHOD(device_probe,		siba_mips_probe),
+
+	{0, 0},
+};
+
+static driver_t siba_mips_driver = {
+	"siba_mips",
+	siba_mips_methods,
+	sizeof(struct siba_softc),
+};
+static devclass_t siba_mips_devclass;
+
+DRIVER_MODULE(siba_mips, siba, siba_mips_driver, siba_mips_devclass, 0, 0);
diff --git a/sys/mips/sentry5/siba_sdram.c b/sys/mips/sentry5/siba_sdram.c
new file mode 100644
index 0000000..8e74e53
--- /dev/null
+++ b/sys/mips/sentry5/siba_sdram.c
@@ -0,0 +1,114 @@
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Child driver for SDRAM/DDR controller core.
+ * Generally the OS should not need to access this device unless the
+ * firmware has not configured the SDRAM controller.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <dev/siba/sibavar.h>
+#include <dev/siba/sibareg.h>
+#include <dev/siba/siba_ids.h>
+
+static int	siba_sdram_attach(device_t);
+static int	siba_sdram_probe(device_t);
+
+static int
+siba_sdram_probe(device_t dev)
+{
+
+	if (siba_get_vendor(dev) == SIBA_VID_BROADCOM &&
+	    siba_get_device(dev) == SIBA_DEVID_SDRAMDDR) {
+		device_set_desc(dev, "SDRAM/DDR core");
+		return (BUS_PROBE_DEFAULT);
+	}
+
+	return (ENXIO);
+}
+
+struct siba_sdram_softc {
+	void *notused;
+};
+
+static int
+siba_sdram_attach(device_t dev)
+{
+	//struct siba_sdram_softc *sc = device_get_softc(dev);
+	struct resource *mem;
+	int rid;
+
+	/*
+	 * Allocate the resources which the parent bus has already
+	 * determined for us.
+	 * TODO: interrupt routing
+	 */
+#define MIPS_MEM_RID 0x20
+	rid = MIPS_MEM_RID;
+	mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+	    RF_ACTIVE);
+	if (mem == NULL) {
+		device_printf(dev, "unable to allocate memory\n");
+		return (ENXIO);
+	}
+
+#if 0
+	device_printf(dev, "start %08lx size %04lx\n",
+	    rman_get_start(mem), rman_get_size(mem));
+#endif
+
+	return (0);
+}
+
+static device_method_t siba_sdram_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_attach,	siba_sdram_attach),
+	DEVMETHOD(device_probe,		siba_sdram_probe),
+
+	{0, 0},
+};
+
+static driver_t siba_sdram_driver = {
+	"siba_sdram",
+	siba_sdram_methods,
+	sizeof(struct siba_softc),
+};
+static devclass_t siba_sdram_devclass;
+
+DRIVER_MODULE(siba_sdram, siba, siba_sdram_driver, siba_sdram_devclass, 0, 0);
diff --git a/sys/mips/sentry5/uart_bus_sbusart.c b/sys/mips/sentry5/uart_bus_sbusart.c
new file mode 100644
index 0000000..e4808cd
--- /dev/null
+++ b/sys/mips/sentry5/uart_bus_sbusart.c
@@ -0,0 +1,95 @@
+/*-
+ * Copyright (c) 2007 Bruce M. Simpson.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/mips32/sentry5/sentry5reg.h>
+
+#include "uart_if.h"
+
+static int uart_malta_probe(device_t dev);
+
+extern struct uart_class malta_uart_class;
+
+static device_method_t uart_malta_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		uart_malta_probe),
+	DEVMETHOD(device_attach,	uart_bus_attach),
+	DEVMETHOD(device_detach,	uart_bus_detach),
+	{ 0, 0 }
+};
+
+static driver_t uart_malta_driver = {
+	uart_driver_name,
+	uart_malta_methods,
+	sizeof(struct uart_softc),
+};
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+static int
+uart_malta_probe(device_t dev)
+{
+	struct uart_softc *sc;
+
+	sc = device_get_softc(dev);
+	sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+	sc->sc_class = &uart_ns8250_class;
+	bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+	sc->sc_sysdev->bas.bst = 0;
+	sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
+	sc->sc_bas.bst = 0;
+	sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
+	return(uart_bus_probe(dev, 0, 0, 0, 0));
+}
+
+DRIVER_MODULE(uart, obio, uart_malta_driver, uart_devclass, 0, 0);
diff --git a/sys/mips/sentry5/uart_cpu_sbusart.c b/sys/mips/sentry5/uart_cpu_sbusart.c
new file mode 100644
index 0000000..e1da9b2
--- /dev/null
+++ b/sys/mips/sentry5/uart_cpu_sbusart.c
@@ -0,0 +1,82 @@
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/mips32/sentry5/sentry5reg.h>
+
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+extern struct uart_ops malta_usart_ops;
+extern struct bus_space malta_bs_tag;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+	return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+	di->ops = uart_getops(&uart_ns8250_class);
+	di->bas.chan = 0;
+	di->bas.bst = 0;
+	di->bas.regshft = 0;
+	di->bas.rclk = 0;
+	di->baudrate = 115200;
+	di->databits = 8;
+	di->stopbits = 1;
+	di->parity = UART_PARITY_NONE;
+
+	uart_bus_space_io = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
+	uart_bus_space_mem = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
+	di->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
+	return (0);
+}