MIPS changes for Netlogic XLP support.

This patch adds support for the Netlogic XLP mips64 processors in
the common MIPS code. The changes are :

- Add CPU_NLM processor type
- Add cases for CPU_NLM, mostly were CPU_RMI is used.
- Update cache flush changes for CPU_NLM
- Add kernel build configuration files for xLP.

In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com>

Approved by:	bz(re), jmallett, imp(mips)

3 files changed, 8 insertions, 17 deletions

diff --git a/sys/mips/nlm/cms.c b/sys/mips/nlm/cms.c
index c8a06f2..fb03d80 100644
--- a/sys/mips/nlm/cms.c
+++ b/sys/mips/nlm/cms.c
@@ -257,13 +257,14 @@ xlp_handle_msg_vc(int vc, int max_msgs)
 			continue;
 		}
 		he = &msgmap[srcid];
-		if(he->action == NULL) {
+		if(he->action != NULL)
+			(he->action)(vc, size, code, srcid, &msg, he->arg);
+#if 0 /* debug */
+		else
 			printf("[%s]: No Handler for message from stn_id=%d,"
 			    " vc=%d, size=%d, msg0=%jx, dropping message\n",
 			    __func__, srcid, vc, size, (uintmax_t)msg.msg[0]);
-			continue;
-		}
-		(he->action)(vc, size, code, srcid, &msg, he->arg);
+#endif
 	}
 
 	return (i);
diff --git a/sys/mips/nlm/std.xlp b/sys/mips/nlm/std.xlp
index 7b5eed5..01c9245 100644
--- a/sys/mips/nlm/std.xlp
+++ b/sys/mips/nlm/std.xlp
@@ -1,12 +1,4 @@
 # $FreeBSD$
 files	"../nlm/files.xlp"
-cpu	CPU_NLMXLP
+cpu	CPU_NLM
 
-#
-# XXXMIPS: It's a stub, isn't it?
-#
-#option	HW_PAGEWALKER
-#option	MMU_HASH_MODE  # enables hash based lookup into extended TLBs
-#option	MMU_CLOCK_GATING # enables clock gating on MMU
-#option	MMU_GLOBAL_MODE  # enables global mode of sharing all TLBs with all h/w threads
-#option	NOFPU
diff --git a/sys/mips/nlm/xlp_machdep.c b/sys/mips/nlm/xlp_machdep.c
index 4bf92462..6b4bde4 100644
--- a/sys/mips/nlm/xlp_machdep.c
+++ b/sys/mips/nlm/xlp_machdep.c
@@ -214,8 +214,7 @@ xlp_parse_mmu_options(void)
 
 unsupp:
 	printf("ERROR : Unsupported CPU mask [use 1,2 or 4 threads per core].\n"
-	    "\tcore0 thread mask [%lx], boot cpu mask [%lx]\n"
-	    "\tUsing default, 16 TLB entries per CPU, split mode\n", 
+	    "\tcore0 thread mask [%lx], boot cpu mask [%lx].\n",
 	    (u_long)core0_thr_mask, (u_long)cpu_map);
 	panic("Invalid CPU mask - halting.\n");
 	return;
@@ -495,8 +494,6 @@ platform_start(__register_t a0 __unused,
 	xlp_pic_init();
 
 	mips_timer_init_params(xlp_cpu_frequency, 0);
-
-	printf("Platform specific startup now completes\n");
 }
 
 void 
@@ -630,6 +627,7 @@ platform_ipi_intrnum(void)
 void
 platform_ipi_send(int cpuid)
 {
+
 	nlm_pic_send_ipi(xlp_pic_base, 0, xlp_cpuid_to_hwtid[cpuid],
 	    platform_ipi_intrnum(), 0);
 }