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| author | jchandra <jchandra@FreeBSD.org> | 2011-01-13 15:17:29 +0000 |
|---|---|---|
| committer | jchandra <jchandra@FreeBSD.org> | 2011-01-13 15:17:29 +0000 |
| commit | 564c9a855eee850b6f252549bbb5ec6af6ba778a (patch) | |
| tree | 088c80e0e190da6dd7f15ceb0535eecfaf39addf /sys/mips/mips/swtch.S | |
| parent | 267bbb010596a8758a3d64f44dc570be2e5ed5aa (diff) | |
| download | FreeBSD-src-564c9a855eee850b6f252549bbb5ec6af6ba778a.zip FreeBSD-src-564c9a855eee850b6f252549bbb5ec6af6ba778a.tar.gz | |
Support for 64 bit PTEs on n32 and n64 compilation.
In n32 and n64, add support for physical address above 4GB by having
64 bit page table entries and physical addresses. Major changes are:
- param.h: update PTE sizes, masks and shift values to support 64 bit PTEs.
- param.h: remove DELAY(), mips_btop(same as atop), mips_ptob (same as
ptoa), and reformat.
- param.h: remove casting to unsigned long in trunc_page and round_page
since this will be used on physical addresses.
- _types.h: have 64 bit __vm_paddr_t for n32.
- pte.h: update TLB LO0/1 access macros to support 64 bit PTE
- pte.h: assembly macros for PTE operations.
- proc.h: md_upte is now 64 bit for n32 and n64.
- exception.S and swtch.S: use the new PTE macros for PTE operations.
- cpufunc.h: TLB_LO0/1 registers are 64bit for n32 and n64.
- xlr_machdep.c: Add memory segments above 4GB to phys_avail[] as they are
supported now.
Reviewed by: jmallett (earlier version)
Diffstat (limited to 'sys/mips/mips/swtch.S')
| -rw-r--r-- | sys/mips/mips/swtch.S | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/sys/mips/mips/swtch.S b/sys/mips/mips/swtch.S index 80c0cab..9390e41 100644 --- a/sys/mips/mips/swtch.S +++ b/sys/mips/mips/swtch.S @@ -91,6 +91,7 @@ #define RESTORE_U_PCB_CONTEXT(reg, offs, base) \ REG_L reg, U_PCB_CONTEXT + (SZREG * offs) (base) + /* * Setup for and return to user. */ @@ -284,8 +285,8 @@ blocked_loop: PTR_LI s0, MIPS_KSEG2_START # If Uarea addr is below kseg2, #endif bltu v0, s0, sw2 # no need to insert in TLB. - lw a1, TD_UPTE + 0(s7) # a1 = u. pte #0 - lw a2, TD_UPTE + 4(s7) # a2 = u. pte #1 + PTE_L a1, TD_UPTE + 0(s7) # a1 = u. pte #0 + PTE_L a2, TD_UPTE + PTESIZE(s7) # a2 = u. pte #1 /* * Wiredown the USPACE of newproc in TLB entry#0. Check whether target * USPACE is already in another place of TLB before that, and if so @@ -306,8 +307,8 @@ blocked_loop: sll s0, PAGE_SHIFT + 1 addu t1, s0 MTC0 t1, MIPS_COP_0_TLB_HI - mtc0 zero, MIPS_COP_0_TLB_LO0 - mtc0 zero, MIPS_COP_0_TLB_LO1 + PTE_MTC0 zero, MIPS_COP_0_TLB_LO0 + PTE_MTC0 zero, MIPS_COP_0_TLB_LO1 HAZARD_DELAY tlbwi HAZARD_DELAY @@ -317,9 +318,9 @@ entry0set: /* SMP!! - Works only for unshared TLB case - i.e. no v-cpus */ mtc0 zero, MIPS_COP_0_TLB_INDEX # TLB entry #0 HAZARD_DELAY - mtc0 a1, MIPS_COP_0_TLB_LO0 # upte[0] + PTE_MTC0 a1, MIPS_COP_0_TLB_LO0 # upte[0] HAZARD_DELAY - mtc0 a2, MIPS_COP_0_TLB_LO1 # upte[1] + PTE_MTC0 a2, MIPS_COP_0_TLB_LO1 # upte[1] HAZARD_DELAY tlbwi # set TLB entry #0 HAZARD_DELAY |
