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| author | jchandra <jchandra@FreeBSD.org> | 2011-11-19 14:14:35 +0000 |
|---|---|---|
| committer | jchandra <jchandra@FreeBSD.org> | 2011-11-19 14:14:35 +0000 |
| commit | 9059cbf57d7290cf1dc4420c04ca61afdc297419 (patch) | |
| tree | 150acf4ff1159462306ac9de790e08832b5bfe34 /sys/mips/mips/cache.c | |
| parent | 751092ac03de2a27db50a384379d53f52133c479 (diff) | |
| download | FreeBSD-src-9059cbf57d7290cf1dc4420c04ca61afdc297419.zip FreeBSD-src-9059cbf57d7290cf1dc4420c04ca61afdc297419.tar.gz | |
Fixup cache flush definitions for XLP
mco_icache_sync_range was earlier set to mipsNN_icache_sync_range_index_32
which is not necessary, revert this.
Also, the data cache is coherent so write back is not really needed. This
change is experimental.
Diffstat (limited to 'sys/mips/mips/cache.c')
| -rw-r--r-- | sys/mips/mips/cache.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/sys/mips/mips/cache.c b/sys/mips/mips/cache.c index 4e7f35f..6483319 100644 --- a/sys/mips/mips/cache.c +++ b/sys/mips/mips/cache.c @@ -101,13 +101,8 @@ mips_config_cache(struct mips_cpuinfo * cpuinfo) break; case 32: mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32; -#ifdef CPU_NLM - mips_cache_ops.mco_icache_sync_range = - mipsNN_icache_sync_range_index_32; -#else mips_cache_ops.mco_icache_sync_range = mipsNN_icache_sync_range_32; -#endif mips_cache_ops.mco_icache_sync_range_index = mipsNN_icache_sync_range_index_32; break; @@ -155,18 +150,23 @@ mips_config_cache(struct mips_cpuinfo * cpuinfo) mips_cache_ops.mco_pdcache_wbinv_all = mips_cache_ops.mco_intern_pdcache_wbinv_all = mipsNN_pdcache_wbinv_all_32; -#ifdef CPU_NLM - mips_cache_ops.mco_pdcache_wbinv_range = - mipsNN_pdcache_wbinv_range_index_32; +#if defined(CPU_RMI) || defined(CPU_NLM) + mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; #else mips_cache_ops.mco_pdcache_wbinv_range = mipsNN_pdcache_wbinv_range_32; #endif +#if defined(CPU_RMI) || defined(CPU_NLM) + mips_cache_ops.mco_pdcache_wbinv_range_index = + mips_cache_ops.mco_intern_pdcache_wbinv_range_index = cache_noop; + mips_cache_ops.mco_pdcache_inv_range = cache_noop; +#else mips_cache_ops.mco_pdcache_wbinv_range_index = mips_cache_ops.mco_intern_pdcache_wbinv_range_index = mipsNN_pdcache_wbinv_range_index_32; mips_cache_ops.mco_pdcache_inv_range = mipsNN_pdcache_inv_range_32; +#endif #if defined(CPU_RMI) || defined(CPU_NLM) mips_cache_ops.mco_pdcache_wb_range = mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; |
