Merge from projects/mips to head by hand:

r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines
Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP.  Provide a missing prototype.

r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines
With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
 making it run ;-)

r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines
Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
   intr_machdep.c.  This allows us to have an architecture dependant
   intr_machdep.c (which we will need for RMI) in the machine specific
   directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
   may need to look at finding a better place to put this. But first I want to
   get this thing compiling.

r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines
- Clean out some XXXMIPS comments that's not relevant now

r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines
Fix style error replicated multiple times.  Move to
mips_bus_space_generic for octeon obio impl.

r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines
Don't force ISA_MIPS32.

r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines
Make the yamon function pointer stuff 64-bit safe.  Make the base
unsigned long, and sign extend the address of the function we're
calling through.

r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines
Addresses should be unsigned long.  Make the address constants
unsigned long.

r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines
- Do not use hardcoded uart speed
- Call mips_timer_early_init before initializing uart in order
    to make DELAY usable for ns8250 driver
Submitted by:	Neelkanth Natu

r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines
- Fix prototypes to make compiler happy

r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines
- Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default
   we assume that there is no FPU, because majority of SoC does
   not have it.

r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines
- Provide proper pre_thread/post_ithread functions for GT PCI
    controller.

r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines
- Make mips_bus_space_generic be of type bus_space_tag_t instead of
    struct bus_space and update all relevant places.

r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines
Use FreeBSD/arm approach for handling bus space access: space tag is a pointer
to bus_space structure that defines access methods and hence every bus can
define own accessors. Default space is mips_bus_space_generic. It's a simple
interface to physical memory, values are read with regard to host system
byte order.

9 files changed, 183 insertions, 123 deletions

diff --git a/sys/mips/malta/files.malta b/sys/mips/malta/files.malta
index 6ade95f..82d9ca4 100644
--- a/sys/mips/malta/files.malta
+++ b/sys/mips/malta/files.malta
@@ -7,3 +7,5 @@ mips/malta/uart_bus_maltausart.c	optional uart
 dev/uart/uart_dev_ns8250.c		optional uart
 mips/malta/malta_machdep.c		standard
 mips/malta/yamon.c			standard
+mips/mips/intr_machdep.c		standard
+mips/mips/tick.c			standard
diff --git a/sys/mips/malta/gt_pci.c b/sys/mips/malta/gt_pci.c
index f0180f6..2f0eada 100644
--- a/sys/mips/malta/gt_pci.c
+++ b/sys/mips/malta/gt_pci.c
@@ -91,11 +91,16 @@ __FBSDID("$FreeBSD$");
 #define OCW3_POLL_IRQ(x) ((x) & 0x7f)
 #define OCW3_POLL_PENDING (1U << 7)
 
+struct gt_pci_softc;
+
+struct gt_pci_intr_cookie {
+	int irq;
+	struct gt_pci_softc *sc;
+};
+
 struct gt_pci_softc {
 	device_t 		sc_dev;
 	bus_space_tag_t 	sc_st;
-	bus_space_tag_t		sc_pciio;
-	bus_space_tag_t		sc_pcimem;
 	bus_space_handle_t	sc_ioh_icu1;
 	bus_space_handle_t	sc_ioh_icu2;
 	bus_space_handle_t	sc_ioh_elcr;
@@ -109,6 +114,7 @@ struct gt_pci_softc {
 
 	struct resource		*sc_irq;
 	struct intr_event	*sc_eventstab[ICU_LEN];
+	struct gt_pci_intr_cookie	sc_intr_cookies[ICU_LEN];
 	uint16_t		sc_imask;
 	uint16_t		sc_elcr;
 
@@ -117,6 +123,52 @@ struct gt_pci_softc {
 	void			*sc_ih;
 };
 
+static void gt_pci_set_icus(struct gt_pci_softc *);
+static int gt_pci_intr(void *v);
+static int gt_pci_probe(device_t);
+static int gt_pci_attach(device_t);
+static int gt_pci_activate_resource(device_t, device_t, int, int, 
+    struct resource *);
+static int gt_pci_setup_intr(device_t, device_t, struct resource *, 
+    int, driver_filter_t *, driver_intr_t *, void *, void **);
+static int gt_pci_teardown_intr(device_t, device_t, struct resource *, void*);
+static int gt_pci_maxslots(device_t );
+static int gt_pci_conf_setup(struct gt_pci_softc *, int, int, int, int, 
+    uint32_t *);
+static uint32_t gt_pci_read_config(device_t, u_int, u_int, u_int, u_int, int);
+static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int, 
+    uint32_t, int);
+static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin);
+static struct resource * gt_pci_alloc_resource(device_t, device_t, int, 
+    int *, u_long, u_long, u_long, u_int);
+
+static void
+gt_pci_mask_irq(void *source)
+{
+	struct gt_pci_intr_cookie *cookie = source;
+	struct gt_pci_softc *sc = cookie->sc;
+	int irq = cookie->irq;
+
+	sc->sc_imask |= (1 << irq);
+	sc->sc_elcr |= (1 << irq);
+
+	gt_pci_set_icus(sc);
+}
+
+static void
+gt_pci_unmask_irq(void *source)
+{
+	struct gt_pci_intr_cookie *cookie = source;
+	struct gt_pci_softc *sc = cookie->sc;
+	int irq = cookie->irq;
+
+	/* Enable it, set trigger mode. */
+	sc->sc_imask &= ~(1 << irq);
+	sc->sc_elcr &= ~(1 << irq);
+
+	gt_pci_set_icus(sc);
+}
+
 static void
 gt_pci_set_icus(struct gt_pci_softc *sc)
 {
@@ -126,14 +178,14 @@ gt_pci_set_icus(struct gt_pci_softc *sc)
 	else
 		sc->sc_imask |= (1U << 2);
 
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1,
 	    sc->sc_imask & 0xff);
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, PIC_OCW1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1,
 	    (sc->sc_imask >> 8) & 0xff);
 
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
 	    sc->sc_elcr & 0xff);
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
 	    (sc->sc_elcr >> 8) & 0xff);
 }
 
@@ -145,9 +197,9 @@ gt_pci_intr(void *v)
 	int irq;
 
 	for (;;) {
-		bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3,
+		bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3,
 		    OCW3_SEL | OCW3_P);
-		irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3);
+		irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3);
 		if ((irq & OCW3_POLL_PENDING) == 0)
 		{
 			return FILTER_HANDLED;
@@ -156,9 +208,9 @@ gt_pci_intr(void *v)
 		irq = OCW3_POLL_IRQ(irq);
 
 		if (irq == 2) {
-			bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2,
+			bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
 			    PIC_OCW3, OCW3_SEL | OCW3_P);
-			irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu2,
+			irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2,
 			    PIC_OCW3);
 			if (irq & OCW3_POLL_PENDING)
 				irq = OCW3_POLL_IRQ(irq) + 8;
@@ -177,13 +229,13 @@ gt_pci_intr(void *v)
 
 		/* Send a specific EOI to the 8259. */
 		if (irq > 7) {
-			bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2,
+			bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
 			    PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
 			    OCW2_ILS(irq & 7));
 			irq = 2;
 		}
 
-		bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW2,
+		bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2,
 		    OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
 	}
 
@@ -208,8 +260,7 @@ gt_pci_attach(device_t dev)
 	busno = 0;
 	sc->sc_dev = dev;
 	sc->sc_busno = busno;
-	sc->sc_pciio = MIPS_BUS_SPACE_IO;
-	sc->sc_pcimem = MIPS_BUS_SPACE_MEM;
+	sc->sc_st = mips_bus_space_generic;
 
 	/* Use KSEG1 to access IO ports for it is uncached */
 	sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE);
@@ -239,11 +290,11 @@ gt_pci_attach(device_t dev)
 	 * Map the PIC/ELCR registers.
 	 */
 #if 0
-	if (bus_space_map(sc->sc_pciio, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
+	if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
 		device_printf(dev, "unable to map ELCR registers\n");
-	if (bus_space_map(sc->sc_pciio, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
+	if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
 		device_printf(dev, "unable to map ICU1 registers\n");
-	if (bus_space_map(sc->sc_pciio, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
+	if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
 		device_printf(dev, "unable to map ICU2 registers\n");
 #else
 	sc->sc_ioh_elcr = sc->sc_io + 0x4d0;
@@ -262,58 +313,58 @@ gt_pci_attach(device_t dev)
 	 * Initialize the 8259s.
 	 */
 	/* reset, program device, 4 bytes */
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
 	    ICW1_RESET | ICW1_IC4);
 	/*
 	 * XXX: values from NetBSD's <dev/ic/i8259reg.h>
 	 */	 
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
 	    0/*XXX*/);
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
 	    1 << 2);
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
 	    ICW4_8086);
 
 	/* mask all interrupts */
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
 	    sc->sc_imask & 0xff);
 
 	/* enable special mask mode */
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
 	    OCW3_SEL | OCW3_ESMM | OCW3_SMM);
 
 	/* read IRR by default */
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
 	    OCW3_SEL | OCW3_RR);
 
 	/* reset, program device, 4 bytes */
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
 	    ICW1_RESET | ICW1_IC4);
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
 	    0/*XXX*/);
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
 	    1 << 2);
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
 	    ICW4_8086);
 
 	/* mask all interrupts */
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
 	    sc->sc_imask & 0xff);
 
 	/* enable special mask mode */
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
 	    OCW3_SEL | OCW3_ESMM | OCW3_SMM);
 
 	/* read IRR by default */
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
 	    OCW3_SEL | OCW3_RR);
 
 	/*
 	 * Default all interrupts to edge-triggered.
 	 */
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
 	    sc->sc_elcr & 0xff);
-	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1,
+	bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
 	    (sc->sc_elcr >> 8) & 0xff);
 
 	/*
@@ -570,12 +621,12 @@ gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
 		break;
 	case SYS_RES_MEMORY:
 		rm = &sc->sc_mem_rman;
-		bt = sc->sc_pcimem;
+		bt = sc->sc_st;
 		bh = sc->sc_mem;
 		break;
 	case SYS_RES_IOPORT:
 		rm = &sc->sc_io_rman;
-		bt = sc->sc_pciio;
+		bt = sc->sc_st;
 		bh = sc->sc_io;
 		break;
 	default:
@@ -632,10 +683,13 @@ gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires,
 		panic("%s: bad irq or type", __func__);
 
 	event = sc->sc_eventstab[irq];
+	sc->sc_intr_cookies[irq].irq = irq;
+	sc->sc_intr_cookies[irq].sc = sc;
 	if (event == NULL) {
-                error = intr_event_create(&event, (void *)irq, 0, irq,
-		    (mask_fn)mips_mask_irq, (mask_fn)mips_unmask_irq,
-		    (mask_fn)mips_unmask_irq, NULL, "gt_pci intr%d:", irq);
+                error = intr_event_create(&event, 
+		    (void *)&sc->sc_intr_cookies[irq], 0, irq,
+		    gt_pci_mask_irq, gt_pci_unmask_irq,
+		    NULL, NULL, "gt_pci intr%d:", irq);
 		if (error)
 			return 0;
 		sc->sc_eventstab[irq] = event;
@@ -644,12 +698,7 @@ gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires,
 	intr_event_add_handler(event, device_get_nameunit(child), filt, 
 	    handler, arg, intr_priority(flags), flags, cookiep);
 
-	/* Enable it, set trigger mode. */
-	sc->sc_imask &= ~(1 << irq);
-	sc->sc_elcr &= ~(1 << irq);
-
-	gt_pci_set_icus(sc);
-
+	gt_pci_unmask_irq((void *)&sc->sc_intr_cookies[irq]);
 	return 0;
 }
 
@@ -657,6 +706,12 @@ static int
 gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
     void *cookie)
 {
+	struct gt_pci_softc *sc = device_get_softc(dev);
+	int irq;
+
+	irq = rman_get_start(res);
+	gt_pci_mask_irq((void *)&sc->sc_intr_cookies[irq]);
+
 	return (intr_event_remove_handler(cookie));
 }
 
diff --git a/sys/mips/malta/malta_machdep.c b/sys/mips/malta/malta_machdep.c
index c5c28af..c596d4f 100644
--- a/sys/mips/malta/malta_machdep.c
+++ b/sys/mips/malta/malta_machdep.c
@@ -97,6 +97,12 @@ static int malta_lcd_offs[] = {
 	MALTA_ASCIIPOS7
 };
 
+void
+platform_cpu_init()
+{
+	/* Nothing special */
+}
+
 /*
  * Put character to Malta LCD at given position.
  */
@@ -226,6 +232,52 @@ platform_trap_exit(void)
 
 }
 
+static uint64_t
+malta_cpu_freq(void)
+{
+	uint64_t platform_counter_freq = 0;
+
+#if defined(TICK_USE_YAMON_FREQ)
+	/*
+	 * If we are running on a board which uses YAMON firmware,
+	 * then query CPU pipeline clock from the syscon object.
+	 * If unsuccessful, use hard-coded default.
+	 */
+	platform_counter_freq = yamon_getcpufreq();
+
+#elif defined(TICK_USE_MALTA_RTC)
+	/*
+	 * If we are running on a board with the MC146818 RTC,
+	 * use it to determine CPU pipeline clock frequency.
+	 */
+	u_int64_t counterval[2];
+
+	/* Set RTC to binary mode. */
+	writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD));
+
+	/* Busy-wait for falling edge of RTC update. */
+	while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
+		;
+	while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
+		;
+	counterval[0] = mips_rd_count();
+
+	/* Busy-wait for falling edge of RTC update. */
+	while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
+		;
+	while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
+		;
+	counterval[1] = mips_rd_count();
+
+	platform_counter_freq = counterval[1] - counterval[0];
+#endif
+
+	if (platform_counter_freq == 0)
+		platform_counter_freq = MIPS_DEFAULT_HZ;
+
+	return (platform_counter_freq);
+}
+
 void
 platform_start(__register_t a0, __register_t a1,  __register_t a2, 
     __register_t a3)
@@ -242,6 +294,10 @@ platform_start(__register_t a0, __register_t a1,  __register_t a2,
 	kernend = round_page((vm_offset_t)&end);
 	memset(&edata, 0, kernend - (vm_offset_t)(&edata));
 
+	mips_pcpu0_init();
+	platform_counter_freq = malta_cpu_freq();
+	mips_timer_early_init(platform_counter_freq);
+
 	cninit();
 	printf("entry: platform_start()\n");
 
@@ -262,44 +318,5 @@ platform_start(__register_t a0, __register_t a1,  __register_t a2,
 	realmem = btoc(memsize);
 	mips_init();
 
-	do {
-#if defined(TICK_USE_YAMON_FREQ)
-		/*
-		 * If we are running on a board which uses YAMON firmware,
-		 * then query CPU pipeline clock from the syscon object.
-		 * If unsuccessful, use hard-coded default.
-		 */
-		platform_counter_freq = yamon_getcpufreq();
-		if (platform_counter_freq == 0)
-			platform_counter_freq = MIPS_DEFAULT_HZ;
-
-#elif defined(TICK_USE_MALTA_RTC)
-		/*
-		 * If we are running on a board with the MC146818 RTC,
-		 * use it to determine CPU pipeline clock frequency.
-		 */
-		u_int64_t counterval[2];
-
-		/* Set RTC to binary mode. */
-		writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD));
-
-		/* Busy-wait for falling edge of RTC update. */
-		while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
-			;
-		while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
-			;
-		counterval[0] = mips_rd_count();
-
-		/* Busy-wait for falling edge of RTC update. */
-		while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
-			;
-		while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
-			;
-		counterval[1] = mips_rd_count();
-
-		platform_counter_freq = counterval[1] - counterval[0];
-#endif
-	} while(0);
-
 	mips_timer_init_params(platform_counter_freq, 0);
 }
diff --git a/sys/mips/malta/maltareg.h b/sys/mips/malta/maltareg.h
index f2a7d08..c311d30 100644
--- a/sys/mips/malta/maltareg.h
+++ b/sys/mips/malta/maltareg.h
@@ -94,37 +94,37 @@
 		15	Secondary IDE	Secondary IDE slot/Compact flash connector
  */
 
-#define	MALTA_SYSTEMRAM_BASE	0x00000000  /* System RAM:	*/
+#define	MALTA_SYSTEMRAM_BASE	0x00000000ul  /* System RAM:	*/
 #define	MALTA_SYSTEMRAM_SIZE	0x08000000  /*   128 MByte	*/
 
-#define	MALTA_PCIMEM1_BASE	0x08000000  /* PCI 1 memory:	*/
+#define	MALTA_PCIMEM1_BASE	0x08000000ul  /* PCI 1 memory:	*/
 #define	MALTA_PCIMEM1_SIZE	0x08000000  /*   128 MByte	*/
 
-#define	MALTA_PCIMEM2_BASE	0x10000000  /* PCI 2 memory:	*/
+#define	MALTA_PCIMEM2_BASE	0x10000000ul  /* PCI 2 memory:	*/
 #define	MALTA_PCIMEM2_SIZE	0x08000000  /*   128 MByte	*/
 
-#define	MALTA_PCIMEM3_BASE	0x18000000  /* PCI 3 memory	*/
+#define	MALTA_PCIMEM3_BASE	0x18000000ul  /* PCI 3 memory	*/
 #define	MALTA_PCIMEM3_SIZE	0x03e00000  /*    62 MByte	*/
 
-#define	MALTA_CORECTRL_BASE	0x1be00000  /* Core control:	*/
+#define	MALTA_CORECTRL_BASE	0x1be00000ul  /* Core control:	*/
 #define	MALTA_CORECTRL_SIZE	0x00200000  /*     2 MByte	*/
 
-#define	MALTA_RESERVED_BASE1	0x1c000000  /* Reserved:	*/
+#define	MALTA_RESERVED_BASE1	0x1c000000ul  /* Reserved:	*/
 #define	MALTA_RESERVED_SIZE1	0x02000000  /*    32 MByte	*/
 
-#define	MALTA_MONITORFLASH_BASE	0x1e000000  /* Monitor Flash:	*/
+#define	MALTA_MONITORFLASH_BASE	0x1e000000ul  /* Monitor Flash:	*/
 #define	MALTA_MONITORFLASH_SIZE	0x003e0000  /*     4 MByte	*/
 #define	MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
 
-#define	MALTA_FILEFLASH_BASE	0x1e3e0000 /* File Flash (for monitor): */
+#define	MALTA_FILEFLASH_BASE	0x1e3e0000ul /* File Flash (for monitor): */
 #define	MALTA_FILEFLASH_SIZE	0x00020000 /*   128 KByte	*/
 
 #define	MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB	*/
 
-#define	MALTA_RESERVED_BASE2	0x1e400000  /* Reserved:	*/
+#define	MALTA_RESERVED_BASE2	0x1e400000ul  /* Reserved:	*/
 #define	MALTA_RESERVED_SIZE2	0x00c00000  /*    12 MByte	*/
 
-#define	MALTA_FPGA_BASE		0x1f000000  /* FPGA:		*/
+#define	MALTA_FPGA_BASE		0x1f000000ul  /* FPGA:		*/
 #define	MALTA_FPGA_SIZE		0x00c00000  /*    12 MByte	*/
 
 #define	MALTA_NMISTATUS		(MALTA_FPGA_BASE + 0x24)
@@ -191,10 +191,10 @@
 #define	MALTA_I2COUT		0x10
 #define	MALTA_I2CSEL		0x18
 
-#define	MALTA_BOOTROM_BASE	0x1fc00000  /* Boot ROM:	*/
+#define	MALTA_BOOTROM_BASE	0x1fc00000ul  /* Boot ROM:	*/
 #define	MALTA_BOOTROM_SIZE	0x00400000  /*     4 MByte	*/
 
-#define	MALTA_REVISION		0x1fc00010
+#define	MALTA_REVISION		0x1fc00010ul
 #define	 MALTA_REV_FPGRV	 0xff0000	/* CBUS FPGA revision */
 #define	 MALTA_REV_CORID	 0x00fc00	/* Core Board ID */
 #define	 MALTA_REV_CORRV	 0x000300	/* Core Board Revision */
diff --git a/sys/mips/malta/obio.c b/sys/mips/malta/obio.c
index ae486ed..2195837 100644
--- a/sys/mips/malta/obio.c
+++ b/sys/mips/malta/obio.c
@@ -63,20 +63,18 @@ int	obio_attach(device_t);
  * A bit tricky and hackish. Since we need OBIO to rely
  * on PCI we make it pseudo-pci device. But there should 
  * be only one such device, so we use this static flag 
- * to prevent false positives on every realPCI device probe. 
+ * to prevent false positives on every real PCI device probe.
  */
 static int have_one = 0;
 
 int
 obio_probe(device_t dev)
 {
-	if(!have_one)
-	{
+	if (!have_one) {
 		have_one = 1;
 		return 0;
 	}
-	else
-		return (ENXIO);
+	return (ENXIO);
 }
 
 int
@@ -84,7 +82,7 @@ obio_attach(device_t dev)
 {
 	struct obio_softc *sc = device_get_softc(dev);
 
-	sc->oba_st = MIPS_BUS_SPACE_IO;
+	sc->oba_st = mips_bus_space_generic;
 	sc->oba_addr = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
 	sc->oba_size = MALTA_PCIMEM3_SIZE;
 	sc->oba_rman.rm_type = RMAN_ARRAY;
diff --git a/sys/mips/malta/std.malta b/sys/mips/malta/std.malta
index ca67e56..6035c32 100644
--- a/sys/mips/malta/std.malta
+++ b/sys/mips/malta/std.malta
@@ -2,8 +2,7 @@
 files	"../malta/files.malta"
 
 cpu		CPU_MIPS4KC
-options 	ISA_MIPS32
-options		SOFTFLOAT
+#options 	ISA_MIPS32
 device		pci
 device		ata
 device		atadisk
diff --git a/sys/mips/malta/uart_bus_maltausart.c b/sys/mips/malta/uart_bus_maltausart.c
index da266a8..e075fff 100644
--- a/sys/mips/malta/uart_bus_maltausart.c
+++ b/sys/mips/malta/uart_bus_maltausart.c
@@ -28,10 +28,6 @@
  * code written by Olivier Houchard.
  */
 
-/*
- * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
- * experimental and was written for MIPS32 port.
- */
 #include "opt_uart.h"
 
 #include <sys/cdefs.h>
@@ -53,9 +49,6 @@ __FBSDID("$FreeBSD$");
 #include <dev/uart/uart_bus.h>
 #include <dev/uart/uart_cpu.h>
 
-/*
- * XXXMIPS:
- */
 #include <mips/malta/maltareg.h>
 
 #include "uart_if.h"
@@ -88,9 +81,9 @@ uart_malta_probe(device_t dev)
 	sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
 	sc->sc_class = &uart_ns8250_class;
 	bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
-	sc->sc_sysdev->bas.bst = 0;
+	sc->sc_sysdev->bas.bst = mips_bus_space_generic;
 	sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
-	sc->sc_bas.bst = 0;
+	sc->sc_bas.bst = mips_bus_space_generic;
 	sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
 	return(uart_bus_probe(dev, 0, 0, 0, 0));
 }
diff --git a/sys/mips/malta/uart_cpu_maltausart.c b/sys/mips/malta/uart_cpu_maltausart.c
index 758d9a7..07ea548 100644
--- a/sys/mips/malta/uart_cpu_maltausart.c
+++ b/sys/mips/malta/uart_cpu_maltausart.c
@@ -29,10 +29,6 @@
  * Skeleton of this file was based on respective code for ARM
  * code written by Olivier Houchard.
  */
-/*
- * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
- * experimental and was written for MIPS32 port.
- */
 #include "opt_uart.h"
 
 #include <sys/cdefs.h>
@@ -67,16 +63,16 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
 {
 	di->ops = uart_getops(&uart_ns8250_class);
 	di->bas.chan = 0;
-	di->bas.bst = 0;
+	di->bas.bst = mips_bus_space_generic;
+	di->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
 	di->bas.regshft = 0;
 	di->bas.rclk = 0;
-	di->baudrate = 115200;
+	di->baudrate = 0;	/* retain the baudrate configured by YAMON */
 	di->databits = 8;
 	di->stopbits = 1;
 	di->parity = UART_PARITY_NONE;
 
-	uart_bus_space_io = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
-	uart_bus_space_mem = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
-	di->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
+	uart_bus_space_io = NULL;
+	uart_bus_space_mem = mips_bus_space_generic;
 	return (0);
 }
diff --git a/sys/mips/malta/yamon.h b/sys/mips/malta/yamon.h
index 6970510..f039ae8 100644
--- a/sys/mips/malta/yamon.h
+++ b/sys/mips/malta/yamon.h
@@ -38,7 +38,7 @@
 #ifndef _MALTA_YAMON_H_
 #define _MALTA_YAMON_H_
 
-#define YAMON_FUNCTION_BASE	0x1fc00500
+#define YAMON_FUNCTION_BASE	0x1fc00500ul
 
 #define YAMON_PRINT_COUNT_OFS	(YAMON_FUNCTION_BASE + 0x04)
 #define YAMON_EXIT_OFS		(YAMON_FUNCTION_BASE + 0x20)
@@ -53,7 +53,7 @@
 #define YAMON_GETCHAR_OFS	(YAMON_FUNCTION_BASE + 0x50)
 #define YAMON_SYSCON_READ_OFS	(YAMON_FUNCTION_BASE + 0x54)
 
-#define YAMON_FUNC(ofs)		(*(uint32_t *)(MIPS_PHYS_TO_KSEG0(ofs)))
+#define YAMON_FUNC(ofs)		((long)(*(int32_t *)(MIPS_PHYS_TO_KSEG0(ofs))))
 
 typedef void (*t_yamon_print_count)(uint32_t port, char *s, uint32_t count);
 #define YAMON_PRINT_COUNT(s, count) \