As discussed on IRC and at BSDcan, move the mips32/* directories up a

level.  The distinction was artificial.  Some more movement around the
deck charis is likely depending on the fallout from this one.

Paths were corrected after the svn mv.  Hope that's OK.

14 files changed, 2163 insertions, 0 deletions

diff --git a/sys/mips/malta/files.malta b/sys/mips/malta/files.malta
new file mode 100644
index 0000000..14bcac1
--- /dev/null
+++ b/sys/mips/malta/files.malta
@@ -0,0 +1,9 @@
+# $FreeBSD$
+mips/malta/gt.c				standard
+mips/malta/gt_pci.c			standard
+mips/malta/obio.c			optional uart
+mips/malta/uart_cpu_maltausart.c		optional uart
+mips/malta/uart_bus_maltausart.c		optional uart
+dev/uart/uart_dev_ns8250.c                      optional uart
+mips/malta/malta_machdep.c		standard
+mips/malta/yamon.c			standard
diff --git a/sys/mips/malta/gt.c b/sys/mips/malta/gt.c
new file mode 100644
index 0000000..daa9e25
--- /dev/null
+++ b/sys/mips/malta/gt.c
@@ -0,0 +1,131 @@
+/*-
+ * Copyright (c) 2005 Olivier Houchard.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/types.h>
+
+#include <vm/vm.h>
+#include <vm/vm_kern.h>
+#include <vm/pmap.h>
+#include <vm/vm_page.h>
+#include <vm/vm_extern.h>
+
+#include <dev/ic/i8259.h>
+
+#include <machine/bus.h>
+#include <machine/intr_machdep.h>
+
+#include <mips/mips32/malta/gtvar.h>
+
+static int
+gt_probe(device_t dev)
+{
+	device_set_desc(dev, "GT64120 chip");
+	return (0);
+}
+
+static void
+gt_identify(driver_t *drv, device_t parent)
+{
+	BUS_ADD_CHILD(parent, 0, "gt", 0);
+}
+
+static int
+gt_attach(device_t dev)
+{
+	struct gt_softc *sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	device_add_child(dev, "pcib", 0);
+	bus_generic_probe(dev);
+	bus_generic_attach(dev);
+
+
+	return (0);
+}
+
+static struct resource *
+gt_alloc_resource(device_t dev, device_t child, int type, int *rid,
+    u_long start, u_long end, u_long count, u_int flags)
+{
+	return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
+		    type, rid, start, end, count, flags));
+	
+}
+
+static int
+gt_setup_intr(device_t dev, device_t child,
+    struct resource *ires, int flags, driver_filter_t *filt, 
+    driver_intr_t *intr, void *arg, void **cookiep)
+{
+	return BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 
+	    filt, intr, arg, cookiep);
+}
+
+static int
+gt_teardown_intr(device_t dev, device_t child, struct resource *res,
+    void *cookie)
+{
+	return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
+}
+
+static int
+gt_activate_resource(device_t dev, device_t child, int type, int rid,
+    struct resource *r)
+{
+	return (BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child,
+		    type, rid, r));
+}
+
+static device_method_t gt_methods[] = {
+	DEVMETHOD(device_probe, gt_probe),
+	DEVMETHOD(device_identify, gt_identify),
+	DEVMETHOD(device_attach, gt_attach),
+
+	DEVMETHOD(bus_setup_intr, gt_setup_intr),
+	DEVMETHOD(bus_teardown_intr, gt_teardown_intr),
+	DEVMETHOD(bus_alloc_resource, gt_alloc_resource),
+	DEVMETHOD(bus_activate_resource, gt_activate_resource),
+	DEVMETHOD(bus_print_child,	bus_generic_print_child),
+
+	{0, 0},
+};
+
+static driver_t gt_driver = {
+	"gt",
+	gt_methods,
+	sizeof(struct gt_softc),
+};
+static devclass_t gt_devclass;
+
+DRIVER_MODULE(gt, nexus, gt_driver, gt_devclass, 0, 0);
diff --git a/sys/mips/malta/gt_pci.c b/sys/mips/malta/gt_pci.c
new file mode 100644
index 0000000..2521058
--- /dev/null
+++ b/sys/mips/malta/gt_pci.c
@@ -0,0 +1,723 @@
+/*	$NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $	*/
+
+/*-
+ * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * PCI configuration support for gt I/O Processor chip.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/pmap.h>
+
+#include <mips/mips32/malta/maltareg.h>
+
+#include <mips/mips32/malta/gtreg.h>
+#include <mips/mips32/malta/gtvar.h>
+
+#include <isa/isareg.h>
+#include <dev/ic/i8259.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <dev/pci/pcib_private.h>
+#include "pcib_if.h"
+
+
+#define	ICU_LEN		16	/* number of ISA IRQs */
+
+/*
+ * XXX: These defines are from NetBSD's <dev/ic/i8259reg.h>. Respective file
+ * from FreeBSD src tree <dev/ic/i8259.h> lacks some definitions.
+ */
+#define PIC_OCW1	1
+#define PIC_OCW2	0
+#define PIC_OCW3	0
+
+#define OCW2_SELECT	0
+#define OCW2_ILS(x)     ((x) << 0)      /* interrupt level select */
+
+#define OCW3_POLL_IRQ(x) ((x) & 0x7f)
+#define OCW3_POLL_PENDING (1U << 7)
+
+struct gt_pci_softc {
+	device_t 		sc_dev;
+	bus_space_tag_t 	sc_st;
+	bus_space_tag_t		sc_pciio;
+	bus_space_tag_t		sc_pcimem;
+	bus_space_handle_t	sc_ioh_icu1;
+	bus_space_handle_t	sc_ioh_icu2;
+	bus_space_handle_t	sc_ioh_elcr;
+
+	int			sc_busno;
+	struct rman		sc_mem_rman;
+	struct rman		sc_io_rman;
+	struct rman		sc_irq_rman;
+	uint32_t		sc_mem;
+	uint32_t		sc_io;
+
+	struct resource		*sc_irq;
+	struct intr_event	*sc_eventstab[ICU_LEN];
+	uint16_t		sc_imask;
+	uint16_t		sc_elcr;
+
+	uint16_t		sc_reserved;
+
+	void			*sc_ih;
+};
+
+static void
+gt_pci_set_icus(struct gt_pci_softc *sc)
+{
+	/* Enable the cascade IRQ (2) if 8-15 is enabled. */
+	if ((sc->sc_imask & 0xff00) != 0xff00)
+		sc->sc_imask &= ~(1U << 2);
+	else
+		sc->sc_imask |= (1U << 2);
+
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW1,
+	    sc->sc_imask & 0xff);
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, PIC_OCW1,
+	    (sc->sc_imask >> 8) & 0xff);
+
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0,
+	    sc->sc_elcr & 0xff);
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1,
+	    (sc->sc_elcr >> 8) & 0xff);
+}
+
+static int
+gt_pci_intr(void *v)
+{
+	struct gt_pci_softc *sc = v;
+	struct intr_event *event;
+	struct intr_handler *ih;
+	int irq, thread;
+
+	for (;;) {
+		bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3,
+		    OCW3_SEL | OCW3_P);
+		irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3);
+		if ((irq & OCW3_POLL_PENDING) == 0)
+		{
+			return FILTER_HANDLED;
+		}
+
+		irq = OCW3_POLL_IRQ(irq);
+
+		if (irq == 2) {
+			bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2,
+			    PIC_OCW3, OCW3_SEL | OCW3_P);
+			irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu2,
+			    PIC_OCW3);
+			if (irq & OCW3_POLL_PENDING)
+				irq = OCW3_POLL_IRQ(irq) + 8;
+			else
+				irq = 2;
+		}
+
+		event = sc->sc_eventstab[irq];
+		thread = 0;
+
+		if (event && !TAILQ_EMPTY(&event->ie_handlers))
+		{
+			/* Execute fast handlers. */
+			TAILQ_FOREACH(ih, &event->ie_handlers, ih_next) {
+				if (ih->ih_filter == NULL)
+					thread = 1;
+				else
+					ih->ih_filter(ih->ih_argument);
+			}
+		}
+
+		/* Schedule thread if needed. */
+		if (thread)
+			intr_event_schedule_thread(event);
+
+		/* Send a specific EOI to the 8259. */
+		if (irq > 7) {
+			bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2,
+			    PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
+			    OCW2_ILS(irq & 7));
+			irq = 2;
+		}
+
+		bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW2,
+		    OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
+	}
+
+	return FILTER_HANDLED;
+}
+
+static int
+gt_pci_probe(device_t dev)
+{
+	device_set_desc(dev, "GT64120 PCI bridge");
+	return (0);
+}
+
+static int
+gt_pci_attach(device_t dev)
+{
+
+	uint32_t busno;				       
+	struct gt_pci_softc *sc = device_get_softc(dev);
+	int rid;
+
+	busno = 0;
+	sc->sc_dev = dev;
+	sc->sc_busno = busno;
+	sc->sc_pciio = MIPS_BUS_SPACE_IO;
+	sc->sc_pcimem = MIPS_BUS_SPACE_MEM;
+
+	/* Use KSEG1 to access IO ports for it is uncached */
+	sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE);
+	sc->sc_io_rman.rm_type = RMAN_ARRAY;
+	sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports";
+	if (rman_init(&sc->sc_io_rman) != 0 ||
+		rman_manage_region(&sc->sc_io_rman, 0, 0xffff) != 0) {
+		panic("gt_pci_attach: failed to set up I/O rman");
+	}
+
+	/* Use KSEG1 to access PCI memory for it is uncached */
+	sc->sc_mem = MIPS_PHYS_TO_KSEG1(MALTA_PCIMEM1_BASE);
+	sc->sc_mem_rman.rm_type = RMAN_ARRAY;
+	sc->sc_mem_rman.rm_descr = "GT64120 PCI Memory";
+	if (rman_init(&sc->sc_mem_rman) != 0 ||
+	    rman_manage_region(&sc->sc_mem_rman, 
+	    sc->sc_mem, sc->sc_mem + MALTA_PCIMEM1_SIZE) != 0) {
+		panic("gt_pci_attach: failed to set up memory rman");
+	}
+	sc->sc_irq_rman.rm_type = RMAN_ARRAY;
+	sc->sc_irq_rman.rm_descr = "GT64120 PCI IRQs";
+	if (rman_init(&sc->sc_irq_rman) != 0 ||
+	    rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
+		panic("gt_pci_attach: failed to set up IRQ rman");
+
+	/*
+	 * Map the PIC/ELCR registers.
+	 */
+#if 0
+	if (bus_space_map(sc->sc_pciio, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
+		device_printf(dev, "unable to map ELCR registers\n");
+	if (bus_space_map(sc->sc_pciio, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
+		device_printf(dev, "unable to map ICU1 registers\n");
+	if (bus_space_map(sc->sc_pciio, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
+		device_printf(dev, "unable to map ICU2 registers\n");
+#else
+	sc->sc_ioh_elcr = sc->sc_io + 0x4d0;
+	sc->sc_ioh_icu1 = sc->sc_io + IO_ICU1;
+	sc->sc_ioh_icu2 = sc->sc_io + IO_ICU2;
+#endif	
+
+
+	/* All interrupts default to "masked off". */
+	sc->sc_imask = 0xffff;
+
+	/* All interrupts default to edge-triggered. */
+	sc->sc_elcr = 0;
+
+	/*
+	 * Initialize the 8259s.
+	 */
+	/* reset, program device, 4 bytes */
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0,
+	    ICW1_RESET | ICW1_IC4);
+	/*
+	 * XXX: values from NetBSD's <dev/ic/i8259reg.h>
+	 */	 
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
+	    0/*XXX*/);
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
+	    1 << 2);
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
+	    ICW4_8086);
+
+	/* mask all interrupts */
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0,
+	    sc->sc_imask & 0xff);
+
+	/* enable special mask mode */
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
+	    OCW3_SEL | OCW3_ESMM | OCW3_SMM);
+
+	/* read IRR by default */
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
+	    OCW3_SEL | OCW3_RR);
+
+	/* reset, program device, 4 bytes */
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0,
+	    ICW1_RESET | ICW1_IC4);
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
+	    0/*XXX*/);
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
+	    1 << 2);
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
+	    ICW4_8086);
+
+	/* mask all interrupts */
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0,
+	    sc->sc_imask & 0xff);
+
+	/* enable special mask mode */
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
+	    OCW3_SEL | OCW3_ESMM | OCW3_SMM);
+
+	/* read IRR by default */
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
+	    OCW3_SEL | OCW3_RR);
+
+	/*
+	 * Default all interrupts to edge-triggered.
+	 */
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0,
+	    sc->sc_elcr & 0xff);
+	bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1,
+	    (sc->sc_elcr >> 8) & 0xff);
+
+	/*
+	 * Some ISA interrupts are reserved for devices that
+	 * we know are hard-wired to certain IRQs.
+	 */
+	sc->sc_reserved =
+		(1U << 0) |     /* timer */
+		(1U << 1) |     /* keyboard controller (keyboard) */
+		(1U << 2) |     /* PIC cascade */
+		(1U << 3) |     /* COM 2 */
+		(1U << 4) |     /* COM 1 */
+		(1U << 6) |     /* floppy */
+		(1U << 7) |     /* centronics */
+		(1U << 8) |     /* RTC */
+		(1U << 9) |	/* I2C */
+		(1U << 12) |    /* keyboard controller (mouse) */
+		(1U << 14) |    /* IDE primary */
+		(1U << 15);     /* IDE secondary */
+
+	/* Hook up our interrupt handler. */
+	if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 
+	    MALTA_SOUTHBRIDGE_INTR, MALTA_SOUTHBRIDGE_INTR, 1, 
+	    RF_SHAREABLE | RF_ACTIVE)) == NULL) {
+		device_printf(dev, "unable to allocate IRQ resource\n");
+		return ENXIO;
+	}
+
+	if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
+			    gt_pci_intr, NULL, sc, &sc->sc_ih))) {
+		device_printf(dev, 
+		    "WARNING: unable to register interrupt handler\n");
+		return ENXIO;
+	}
+
+	/* Initialize memory and i/o rmans. */
+	device_add_child(dev, "pci", busno);
+	return (bus_generic_attach(dev));
+}
+
+static int
+gt_pci_maxslots(device_t dev)
+{
+	return (PCI_SLOTMAX);
+}
+
+static int
+gt_pci_conf_setup(struct gt_pci_softc *sc, int bus, int slot, int func,
+    int reg, uint32_t *addr)
+{
+	*addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
+
+	return (0);
+}
+
+static uint32_t
+gt_pci_read_config(device_t dev, int bus, int slot, int func, int reg,
+    int bytes)
+{
+	struct gt_pci_softc *sc = device_get_softc(dev);
+	uint32_t data;
+	uint32_t addr;
+	uint32_t shift, mask;
+
+	if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
+		return (uint32_t)(-1);
+
+	/* Clear cause register bits. */
+	GT_REGVAL(GT_INTR_CAUSE) = 0;
+
+	GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | addr;
+	data = GT_REGVAL(GT_PCI0_CFG_DATA);
+
+	/* Check for master abort. */
+	if (GT_REGVAL(GT_INTR_CAUSE) & (GTIC_MASABORT0 | GTIC_TARABORT0))
+		data = (uint32_t) -1;
+
+	/*
+	 * XXX: We assume that words readed from GT chip are BE.
+	 *	Should we set the mode explicitly during chip
+	 *	Initialization?
+	 */ 
+	switch(reg % 4)
+	{
+	case 3:
+		shift = 24;
+		break;
+	case 2:
+		shift = 16;
+		break;
+	case 1:
+		shift = 8;
+		break;
+	default:
+		shift = 0;
+		break;
+	}	
+
+	switch(bytes)
+	{
+	case 1:
+		mask = 0xff;
+		data = (data >> shift) & mask;
+		break;
+	case 2:
+		mask = 0xffff;
+		if(reg % 4 == 0)
+			data = data & mask;
+		else
+			data = (data >> 16) & mask;
+		break;
+	case 4:
+		break;
+	default:
+		panic("gt_pci_readconfig: wrong bytes count");
+		break;
+	}
+#if 0
+	printf("PCICONF_READ(%02x:%02x.%02x[%04x] -> %02x(%d)\n", 
+	  bus, slot, func, reg, data, bytes);
+#endif
+
+	return (data);
+}
+
+static void
+gt_pci_write_config(device_t dev, int bus, int slot, int func, int reg,
+    uint32_t data, int bytes)
+{
+	struct gt_pci_softc *sc = device_get_softc(dev);
+	uint32_t addr;
+	uint32_t reg_data;
+	uint32_t shift, mask;
+
+	if(bytes != 4)
+	{
+		reg_data = gt_pci_read_config(dev, bus, slot, func, reg, 4);
+
+		/*
+		* XXX: We assume that words readed from GT chip are BE.
+		*	Should we set the mode explicitly during chip
+		*	Initialization?
+		*/ 
+		switch(reg % 4)
+		{
+		case 3:
+			shift = 24;
+			break;
+		case 2:
+			shift = 16;
+			break;
+		case 1:
+			shift = 8;
+			break;
+		default:
+			shift = 0;
+			break;
+		}	
+
+		switch(bytes)
+		{
+		case 1:
+			mask = 0xff;
+			data = (reg_data & ~ (mask << shift)) | (data << shift);
+			break;
+		case 2:
+			mask = 0xffff;
+			if(reg % 4 == 0)
+				data = (reg_data & ~mask) | data;
+			else
+				data = (reg_data & ~ (mask << shift)) | 
+				    (data << shift);
+			break;
+		case 4:
+			break;
+		default:
+			panic("gt_pci_readconfig: wrong bytes count");
+			break;
+		}
+	}
+
+	if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
+		return;
+
+	/* The galileo has problems accessing device 31. */
+	if (bus == 0 && slot == 31)
+		return;
+
+	/* XXX: no support for bus > 0 yet */
+	if (bus > 0)
+		return;
+
+	/* Clear cause register bits. */
+	GT_REGVAL(GT_INTR_CAUSE) = 0;
+
+	GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | addr;
+	GT_REGVAL(GT_PCI0_CFG_DATA) = data;
+}
+
+static int
+gt_pci_route_interrupt(device_t pcib, device_t dev, int pin)
+{
+	int bus;
+	int device;
+	int func;
+	/* struct gt_pci_softc *sc = device_get_softc(pcib); */
+	bus = pci_get_bus(dev);
+	device = pci_get_slot(dev);
+	func = pci_get_function(dev);
+	/* 
+	 * XXXMIPS: We need routing logic. This is just a stub .
+	 */
+	switch (device) {
+	case 9: /*
+		 * PIIX4 IDE adapter. HW IRQ0
+		 */
+		return 0;
+	default:
+		printf("No mapping for %d/%d/%d/%d\n", bus, device, func, pin);
+		
+	}
+	return (0);
+
+}
+
+static int
+gt_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+	struct gt_pci_softc *sc = device_get_softc(dev);
+	switch (which) {
+	case PCIB_IVAR_DOMAIN:
+		*result = 0;
+		return (0);
+	case PCIB_IVAR_BUS:
+		*result = sc->sc_busno;
+		return (0);
+		
+	}
+	return (ENOENT);
+}
+
+static int
+gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
+{
+	struct gt_pci_softc * sc = device_get_softc(dev);
+
+	switch (which) {
+	case PCIB_IVAR_BUS:
+		sc->sc_busno = result;
+		return (0);
+	}
+	return (ENOENT);
+}
+
+static struct resource *
+gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
+    u_long start, u_long end, u_long count, u_int flags)
+{
+	struct gt_pci_softc *sc = device_get_softc(bus);	
+	struct resource *rv = NULL;
+	struct rman *rm;
+	bus_space_tag_t bt = 0;
+	bus_space_handle_t bh = 0;
+
+	switch (type) {
+	case SYS_RES_IRQ:
+		rm = &sc->sc_irq_rman;
+		break;
+	case SYS_RES_MEMORY:
+		rm = &sc->sc_mem_rman;
+		bt = sc->sc_pcimem;
+		bh = sc->sc_mem;
+		break;
+	case SYS_RES_IOPORT:
+		rm = &sc->sc_io_rman;
+		bt = sc->sc_pciio;
+		bh = sc->sc_io;
+		break;
+	default:
+		return (NULL);
+	}
+
+	rv = rman_reserve_resource(rm, start, end, count, flags, child);
+	if (rv == NULL)
+		return (NULL);
+	rman_set_rid(rv, *rid);
+	if (type != SYS_RES_IRQ) {
+		bh += (rman_get_start(rv));
+
+		rman_set_bustag(rv, bt);
+		rman_set_bushandle(rv, bh);
+		if (flags & RF_ACTIVE) {
+			if (bus_activate_resource(child, type, *rid, rv)) {
+				rman_release_resource(rv);
+				return (NULL);
+			}
+		} 
+	}
+	return (rv);
+}
+
+static int
+gt_pci_activate_resource(device_t bus, device_t child, int type, int rid,
+    struct resource *r)
+{
+	bus_space_handle_t p;
+	int error;
+	
+	if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
+		error = bus_space_map(rman_get_bustag(r),
+		    rman_get_bushandle(r), rman_get_size(r), 0, &p);
+		if (error) 
+			return (error);
+		rman_set_bushandle(r, p);
+	}
+	return (rman_activate_resource(r));
+}
+
+static int
+gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires, 
+		int flags, driver_filter_t *filt, driver_intr_t *handler, 
+		void *arg, void **cookiep)
+{
+	struct gt_pci_softc *sc = device_get_softc(dev);
+	struct intr_event *event;
+	int irq, error;
+
+	irq = rman_get_start(ires);
+	if (irq >= ICU_LEN || irq == 2)
+		panic("%s: bad irq or type", __func__);
+
+	event = sc->sc_eventstab[irq];
+	if (event == NULL) {
+                error = intr_event_create(&event, (void *)irq, 0,
+		    (mask_fn)mips_mask_irq, (mask_fn)mips_unmask_irq,
+		    (mask_fn)mips_unmask_irq, NULL, "gt_pci intr%d:", irq);
+		if (error)
+			return 0;
+		sc->sc_eventstab[irq] = event;
+	}
+
+	intr_event_add_handler(event, device_get_nameunit(child), filt, 
+	    handler, arg, intr_priority(flags), flags, cookiep);
+
+	/* Enable it, set trigger mode. */
+	sc->sc_imask &= ~(1 << irq);
+	sc->sc_elcr &= ~(1 << irq);
+
+	gt_pci_set_icus(sc);
+
+	return 0;
+}
+
+static int
+gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
+    void *cookie)
+{
+	return (intr_event_remove_handler(cookie));
+}
+
+static device_method_t gt_pci_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		gt_pci_probe),
+	DEVMETHOD(device_attach,	gt_pci_attach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	DEVMETHOD(device_suspend,	bus_generic_suspend),
+	DEVMETHOD(device_resume,	bus_generic_resume),
+
+	/* Bus interface */
+	DEVMETHOD(bus_print_child,	bus_generic_print_child),
+	DEVMETHOD(bus_read_ivar,	gt_read_ivar),
+	DEVMETHOD(bus_write_ivar,	gt_write_ivar),
+	DEVMETHOD(bus_alloc_resource,	gt_pci_alloc_resource),
+	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
+	DEVMETHOD(bus_activate_resource, gt_pci_activate_resource),
+	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+	DEVMETHOD(bus_setup_intr,	gt_pci_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	gt_pci_teardown_intr),
+
+	/* pcib interface */
+	DEVMETHOD(pcib_maxslots,	gt_pci_maxslots),
+	DEVMETHOD(pcib_read_config,	gt_pci_read_config),
+	DEVMETHOD(pcib_write_config,	gt_pci_write_config),
+	DEVMETHOD(pcib_route_interrupt,	gt_pci_route_interrupt),
+
+	{0, 0}
+};
+
+static driver_t gt_pci_driver = {
+	"pcib",
+	gt_pci_methods,
+	sizeof(struct gt_pci_softc),
+};
+
+static devclass_t gt_pci_devclass;
+
+DRIVER_MODULE(gt_pci, gt, gt_pci_driver, gt_pci_devclass, 0, 0);
diff --git a/sys/mips/malta/gtreg.h b/sys/mips/malta/gtreg.h
new file mode 100644
index 0000000..8fa05a0
--- /dev/null
+++ b/sys/mips/malta/gtreg.h
@@ -0,0 +1,126 @@
+/*	$NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $	*/
+
+/*-
+ * Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+
+
+#define GT_REGVAL(x)	*((volatile u_int32_t *) \
+			    (MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x))))
+
+/* CPU Configuration Register Map */
+#define	GT_CPU_INT	0x000
+#define	GT_MULTIGT	0x120
+
+/* CPU Address Decode Register Map */
+
+/* CPU Error Report Register Map */
+
+/* CPU Sync Barrier Register Map */
+
+/* SDRAM and Device Address Decode Register Map */
+
+/* SDRAM Configuration Register Map */
+
+/* SDRAM Parameters Register Map */
+
+/* ECC Register Map */
+
+/* Device Parameters Register Map */
+
+/* DMA Record Register Map */
+
+/* DMA Arbiter Register Map */
+
+/* Timer/Counter Register Map */
+//#define	GT_TC_0		0x850
+//#define	GT_TC_1		0x854
+//#define	GT_TC_2		0x858
+//#define	GT_TC_3		0x85c
+//#define	GT_TC_CONTROL	0x864
+
+/* PCI Internal Register Map */
+#define	GT_PCI0_CFG_ADDR	0xcf8
+#define	GT_PCI0_CFG_DATA	0xcfc
+#define	GT_PCI0_INTR_ACK	0xc34
+
+/* Interrupts Register Map */
+#define	GT_INTR_CAUSE	0xc18
+#define	 GTIC_INTSUM	 0x00000001
+#define	 GTIC_MEMOUT	 0x00000002
+#define	 GTIC_DMAOUT	 0x00000004
+#define	 GTIC_CPUOUT	 0x00000008
+#define	 GTIC_DMA0COMP	 0x00000010
+#define	 GTIC_DMA1COMP	 0x00000020
+#define	 GTIC_DMA2COMP	 0x00000040
+#define	 GTIC_DMA3COMP	 0x00000080
+#define	 GTIC_T0EXP	 0x00000100
+#define	 GTIC_T1EXP	 0x00000200
+#define	 GTIC_T2EXP	 0x00000400
+#define	 GTIC_T3EXP	 0x00000800
+#define	 GTIC_MASRDERR0	 0x00001000
+#define	 GTIC_SLVWRERR0	 0x00002000
+#define	 GTIC_MASWRERR0	 0x00004000
+#define	 GTIC_SLVRDERR0	 0x00008000
+#define	 GTIC_ADDRERR0	 0x00010000
+#define	 GTIC_MEMERR	 0x00020000
+#define	 GTIC_MASABORT0	 0x00040000
+#define	 GTIC_TARABORT0	 0x00080000
+#define	 GTIC_RETRYCNT0	 0x00100000
+#define	 GTIC_PMCINT_0	 0x00200000
+#define	 GTIC_CPUINT	 0x0c300000
+#define	 GTIC_PCINT	 0xc3000000
+#define	 GTIC_CPUINTSUM	 0x40000000
+#define	 GTIC_PCIINTSUM	 0x80000000
+
+/* PCI Configuration Register Map */
+//#define	GT_PCICONFIGBASE	0
+//#define	GT_PCIDID		BONITO(GT_PCICONFIGBASE + 0x00)
+//#define	GT_PCICMD		BONITO(GT_PCICONFIGBASE + 0x04)
+//#define	GT_PCICLASS		BONITO(GT_PCICONFIGBASE + 0x08)
+//#define	GT_PCILTIMER		BONITO(GT_PCICONFIGBASE + 0x0c)
+//#define	GT_PCIBASE0		BONITO(GT_PCICONFIGBASE + 0x10)
+//#define	GT_PCIBASE1		BONITO(GT_PCICONFIGBASE + 0x14)
+//#define	GT_PCIBASE2		BONITO(GT_PCICONFIGBASE + 0x18)
+//#define	GT_PCIEXPRBASE		BONITO(GT_PCICONFIGBASE + 0x30)
+//#define	GT_PCIINT		BONITO(GT_PCICONFIGBASE + 0x3c)
+
+/* PCI Configuration, Function 1, Register Map */
+
+/* I2O Support Register Map */
diff --git a/sys/mips/malta/gtvar.h b/sys/mips/malta/gtvar.h
new file mode 100644
index 0000000..f7830ef
--- /dev/null
+++ b/sys/mips/malta/gtvar.h
@@ -0,0 +1,36 @@
+/*-
+ * Copyright (c) 2005 Olivier Houchard.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* $FreeBSD$ */
+
+#ifndef _GTVAR_H_
+#define _GTVAR_H_
+
+#include <sys/rman.h>
+
+struct gt_softc {
+	device_t dev;
+};
+
+#endif /* _GTVAR_H_ */
diff --git a/sys/mips/malta/malta_machdep.c b/sys/mips/malta/malta_machdep.c
new file mode 100644
index 0000000..7464c60
--- /dev/null
+++ b/sys/mips/malta/malta_machdep.c
@@ -0,0 +1,305 @@
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/imgact.h>
+#include <sys/bio.h>
+#include <sys/buf.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/cons.h>
+#include <sys/exec.h>
+#include <sys/ucontext.h>
+#include <sys/proc.h>
+#include <sys/kdb.h>
+#include <sys/ptrace.h>
+#include <sys/reboot.h>
+#include <sys/signalvar.h>
+#include <sys/sysent.h>
+#include <sys/sysproto.h>
+#include <sys/user.h>
+
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+#include <vm/vm_pager.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/pmap.h>
+#include <machine/trap.h>
+
+#ifdef TICK_USE_YAMON_FREQ
+#include <mips/mips32/malta/yamon.h>
+#endif
+
+#ifdef TICK_USE_MALTA_RTC
+#include <mips/mips4k/malta/maltareg.h>
+#include <dev/mc146818/mc146818reg.h>
+#include <isa/rtc.h>
+#endif
+
+#include <mips/mips32/malta/maltareg.h>
+
+extern int	*edata;
+extern int	*end;
+
+void	lcd_init(void);
+void	lcd_puts(char *);
+void	malta_reset(void);
+
+/*
+ * Offsets to MALTA LCD characters.
+ */
+static int malta_lcd_offs[] = {
+	MALTA_ASCIIPOS0,
+	MALTA_ASCIIPOS1,
+	MALTA_ASCIIPOS2,
+	MALTA_ASCIIPOS3,
+	MALTA_ASCIIPOS4,
+	MALTA_ASCIIPOS5,
+	MALTA_ASCIIPOS6,
+	MALTA_ASCIIPOS7
+};
+
+/*
+ * Put character to Malta LCD at given position.
+ */
+static void
+malta_lcd_putc(int pos, char c)
+{
+	void *addr;
+	char *ch;
+
+	if (pos < 0 || pos > 7)
+		return;
+	addr = (void *)(MALTA_ASCII_BASE + malta_lcd_offs[pos]);
+	ch = (char *)MIPS_PHYS_TO_KSEG0(addr);
+	*ch = c;
+}
+
+/*
+ * Print given string on LCD.
+ */
+static void
+malta_lcd_print(char *str)
+{
+	int i;
+	
+	if (str == NULL)
+		return;
+
+	for (i = 0; *str != '\0'; i++, str++)
+		malta_lcd_putc(i, *str);
+}
+
+void
+lcd_init(void)
+{
+	malta_lcd_print("FreeBSD_");
+}
+
+void
+lcd_puts(char *s)
+{
+	malta_lcd_print(s);
+}
+
+#ifdef TICK_USE_MALTA_RTC
+static __inline uint8_t
+rtcin(uint8_t addr)
+{
+
+	*((volatile uint8_t *)
+	    MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCADR))) = addr;
+	return (*((volatile uint8_t *)
+	    MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCDAT))));
+}
+
+static __inline void
+writertc(uint8_t addr, uint8_t val)
+{
+
+	*((volatile uint8_t *)
+	    MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCADR))) = addr;
+	*((volatile uint8_t *)
+	    MIPS_PHYS_TO_KSEG1(MALTA_PCI0_ADDR(MALTA_RTCDAT))) = val;
+}
+#endif
+
+static void
+mips_init(void)
+{
+	int i;
+
+	for (i = 0; i < 10; i++) {
+		phys_avail[i] = 0;
+	}
+
+	/* phys_avail regions are in bytes */
+	phys_avail[0] = MIPS_KSEG0_TO_PHYS((vm_offset_t)&end);
+	phys_avail[1] = ctob(realmem);
+
+	physmem = realmem;
+
+	init_param1();
+	init_param2(physmem);
+	mips_cpu_init();
+	pmap_bootstrap();
+	mips_proc0_init();
+	mutex_init();
+#ifdef DDB
+	kdb_init();
+#endif
+}
+
+void
+platform_halt(void)
+{
+
+}
+
+
+void
+platform_identify(void)
+{
+
+}
+
+/*
+ * Perform a board-level soft-reset.
+ * Note that this is not emulated by gxemul.
+ */
+void
+platform_reset(void)
+{
+	char *c;
+
+	c = (char *)MIPS_PHYS_TO_KSEG0(MALTA_SOFTRES);
+	*c = MALTA_GORESET;
+}
+
+void
+platform_trap_enter(void)
+{
+
+}
+
+void
+platform_trap_exit(void)
+{
+
+}
+
+void
+platform_start(__register_t a0, __register_t a1,  __register_t a2, 
+    __register_t a3)
+{
+	vm_offset_t kernend;
+	uint64_t platform_counter_freq;
+	int argc = a0;
+	char **argv = (char **)a1;
+	char **envp = (char **)a2;
+	unsigned int memsize = a3;
+	int i;
+
+	/* clear the BSS and SBSS segments */
+	kernend = round_page((vm_offset_t)&end);
+	memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+
+	cninit();
+	printf("entry: platform_start()\n");
+
+	bootverbose = 1;
+	if (bootverbose) {
+		printf("cmd line: ");
+		for (i = 0; i < argc; i++)
+			printf("%s ", argv[i]);
+		printf("\n");
+
+		printf("envp:\n");
+		for (i = 0; envp[i]; i += 2)
+			printf("\t%s = %s\n", envp[i], envp[i+1]);
+
+		printf("memsize = %08x\n", memsize);
+	}
+
+	realmem = btoc(memsize);
+	mips_init();
+
+	do {
+#if defined(TICK_USE_YAMON_FREQ)
+		/*
+		 * If we are running on a board which uses YAMON firmware,
+		 * then query CPU pipeline clock from the syscon object.
+		 * If unsuccessful, use hard-coded default.
+		 */
+		platform_counter_freq = yamon_getcpufreq();
+		if (platform_counter_freq == 0)
+			platform_counter_freq = MIPS_DEFAULT_HZ;
+
+#elif defined(TICK_USE_MALTA_RTC)
+		/*
+		 * If we are running on a board with the MC146818 RTC,
+		 * use it to determine CPU pipeline clock frequency.
+		 */
+		u_int64_t counterval[2];
+
+		/* Set RTC to binary mode. */
+		writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD));
+
+		/* Busy-wait for falling edge of RTC update. */
+		while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
+			;
+		while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
+			;
+		counterval[0] = mips_rd_count();
+
+		/* Busy-wait for falling edge of RTC update. */
+		while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
+			;
+		while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
+			;
+		counterval[1] = mips_rd_count();
+
+		platform_counter_freq = counterval[1] - counterval[0];
+#endif
+	} while(0);
+
+	mips_timer_init_params(platform_counter_freq, 0);
+}
diff --git a/sys/mips/malta/maltareg.h b/sys/mips/malta/maltareg.h
new file mode 100644
index 0000000..f2a7d08
--- /dev/null
+++ b/sys/mips/malta/maltareg.h
@@ -0,0 +1,243 @@
+/*	$NetBSD: maltareg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $	*/
+
+/*
+ * Copyright 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+	Memory Map
+
+	0000.0000 *	128MB	Typically SDRAM (on Core Board)
+	0800.0000 *	256MB	Typically PCI
+	1800.0000 *	 62MB	Typically PCI
+	1be0.0000 *	  2MB	Typically System controller's internal registers
+	1c00.0000 *	 32MB	Typically not used
+	1e00.0000	  4MB	Monitor Flash
+	1e40.0000	 12MB	reserved
+	1f00.0000	 12MB	Switches
+				LEDs
+				ASCII display
+				Soft reset
+				FPGA revision number
+				CBUS UART (tty2)
+				General Purpose I/O
+				I2C controller
+	1f10.0000 *	 11MB	Typically System Controller specific
+	1fc0.0000	  4MB	Maps to Monitor Flash
+	1fd0.0000 *	  3MB	Typically System Controller specific
+
+		  * depends on implementation of the Core Board and of software
+ */
+
+/*
+	CPU interrupts
+
+		NMI	South Bridge or NMI button
+		 0	South Bridge INTR
+		 1	South Bridge SMI
+		 2	CBUS UART (tty2)
+		 3	COREHI (Core Card)
+		 4	CORELO (Core Card)
+		 5	Not used, driven inactive (typically CPU internal timer interrupt
+
+	IRQ mapping (as used by YAMON)
+
+		0	Timer		South Bridge
+		1	Keyboard	SuperIO
+		2			Reserved by South Bridge (for cascading)
+		3	UART (tty1)	SuperIO
+		4	UART (tty0)	SuperIO
+		5			Not used
+		6	Floppy Disk	SuperIO
+		7	Parallel Port	SuperIO
+		8	Real Time Clock	South Bridge
+		9	I2C bus		South Bridge
+		10	PCI A,B,eth	PCI slot 1..4, Ethernet
+		11	PCI C,audio	PCI slot 1..4, Audio, USB (South Bridge)
+			PCI D,USB
+		12	Mouse		SuperIO
+		13			Reserved by South Bridge
+		14	Primary IDE	Primary IDE slot
+		15	Secondary IDE	Secondary IDE slot/Compact flash connector
+ */
+
+#define	MALTA_SYSTEMRAM_BASE	0x00000000  /* System RAM:	*/
+#define	MALTA_SYSTEMRAM_SIZE	0x08000000  /*   128 MByte	*/
+
+#define	MALTA_PCIMEM1_BASE	0x08000000  /* PCI 1 memory:	*/
+#define	MALTA_PCIMEM1_SIZE	0x08000000  /*   128 MByte	*/
+
+#define	MALTA_PCIMEM2_BASE	0x10000000  /* PCI 2 memory:	*/
+#define	MALTA_PCIMEM2_SIZE	0x08000000  /*   128 MByte	*/
+
+#define	MALTA_PCIMEM3_BASE	0x18000000  /* PCI 3 memory	*/
+#define	MALTA_PCIMEM3_SIZE	0x03e00000  /*    62 MByte	*/
+
+#define	MALTA_CORECTRL_BASE	0x1be00000  /* Core control:	*/
+#define	MALTA_CORECTRL_SIZE	0x00200000  /*     2 MByte	*/
+
+#define	MALTA_RESERVED_BASE1	0x1c000000  /* Reserved:	*/
+#define	MALTA_RESERVED_SIZE1	0x02000000  /*    32 MByte	*/
+
+#define	MALTA_MONITORFLASH_BASE	0x1e000000  /* Monitor Flash:	*/
+#define	MALTA_MONITORFLASH_SIZE	0x003e0000  /*     4 MByte	*/
+#define	MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
+
+#define	MALTA_FILEFLASH_BASE	0x1e3e0000 /* File Flash (for monitor): */
+#define	MALTA_FILEFLASH_SIZE	0x00020000 /*   128 KByte	*/
+
+#define	MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB	*/
+
+#define	MALTA_RESERVED_BASE2	0x1e400000  /* Reserved:	*/
+#define	MALTA_RESERVED_SIZE2	0x00c00000  /*    12 MByte	*/
+
+#define	MALTA_FPGA_BASE		0x1f000000  /* FPGA:		*/
+#define	MALTA_FPGA_SIZE		0x00c00000  /*    12 MByte	*/
+
+#define	MALTA_NMISTATUS		(MALTA_FPGA_BASE + 0x24)
+#define	 MALTA_NMI_SB		 0x2	/* Pending NMI from the South Bridge */
+#define	 MALTA_NMI_ONNMI	 0x1	/* Pending NMI from the ON/NMI push button */
+
+#define	MALTA_NMIACK		(MALTA_FPGA_BASE + 0x104)
+#define	 MALTA_NMIACK_ONNMI	 0x1	/* Write 1 to acknowledge ON/NMI */
+
+#define	MALTA_SWITCH		(MALTA_FPGA_BASE + 0x200)
+#define	 MALTA_SWITCH_MASK	 0xff	/* settings of DIP switch S2 */
+
+#define	MALTA_STATUS		(MALTA_FPGA_BASE + 0x208)
+#define	 MALTA_ST_MFWR		 0x10	/* Monitor Flash is write protected (JP1) */
+#define	 MALTA_S54		 0x08	/* switch S5-4 - set YAMON factory default mode */
+#define	 MALTA_S53		 0x04	/* switch S5-3 */
+#define	 MALTA_BIGEND		 0x02	/* switch S5-2 - big endian mode */
+
+#define	MALTA_JMPRS		(MALTA_FPGA_BASE + 0x210)
+#define	 MALTA_JMPRS_PCICLK	 0x1c	/* PCI clock frequency */
+#define	 MALTA_JMPRS_EELOCK	 0x02	/* I2C EEPROM is write protected */
+
+#define	MALTA_LEDBAR		(MALTA_FPGA_BASE + 0x408)
+#define	MALTA_ASCIIWORD		(MALTA_FPGA_BASE + 0x410)
+#define	MALTA_ASCII_BASE	(MALTA_FPGA_BASE + 0x418)
+#define	MALTA_ASCIIPOS0		0x00
+#define	MALTA_ASCIIPOS1		0x08
+#define	MALTA_ASCIIPOS2		0x10
+#define	MALTA_ASCIIPOS3		0x18
+#define	MALTA_ASCIIPOS4		0x20
+#define	MALTA_ASCIIPOS5		0x28
+#define	MALTA_ASCIIPOS6		0x30
+#define	MALTA_ASCIIPOS7		0x38
+
+#define	MALTA_SOFTRES		(MALTA_FPGA_BASE + 0x500)
+#define	 MALTA_GORESET		 0x42	/* write this to MALTA_SOFTRES for board reset */
+
+/*
+ * BRKRES is the number of milliseconds before a "break" on tty will
+ * trigger a reset.  A value of 0 will disable the reset.
+ */
+#define	MALTA_BRKRES		(MALTA_FPGA_BASE + 0x508)
+#define	 MALTA_BRKRES_MASK	 0xff
+
+#define	MALTA_CBUSUART		(MALTA_FPGA_BASE + 0x900)
+/* 16C550C UART, 8 bit registers on 8 byte boundaries */
+/* RXTX    0x00 */
+/* INTEN   0x08 */
+/* IIFIFO  0x10 */
+/* LCTRL   0x18 */
+/* MCTRL   0x20 */
+/* LSTAT   0x28 */
+/* MSTAT   0x30 */
+/* SCRATCH 0x38 */
+#define	MALTA_CBUSUART_INTR	2
+
+#define	MALTA_GPIO_BASE		(MALTA_FPGA_BASE + 0xa00)
+#define	MALTA_GPOUT		0x0
+#define	MALTA_GPINP		0x8
+
+#define	MALTA_I2C_BASE		(MALTA_FPGA_BASE + 0xb00)
+#define	MALTA_I2CINP		0x00
+#define	MALTA_I2COE		0x08
+#define	MALTA_I2COUT		0x10
+#define	MALTA_I2CSEL		0x18
+
+#define	MALTA_BOOTROM_BASE	0x1fc00000  /* Boot ROM:	*/
+#define	MALTA_BOOTROM_SIZE	0x00400000  /*     4 MByte	*/
+
+#define	MALTA_REVISION		0x1fc00010
+#define	 MALTA_REV_FPGRV	 0xff0000	/* CBUS FPGA revision */
+#define	 MALTA_REV_CORID	 0x00fc00	/* Core Board ID */
+#define	 MALTA_REV_CORRV	 0x000300	/* Core Board Revision */
+#define	 MALTA_REV_PROID	 0x0000f0	/* Product ID */
+#define	 MALTA_REV_PRORV	 0x00000f	/* Product Revision */
+
+/* PCI definitions */
+#define	MALTA_SOUTHBRIDGE_INTR	   0
+
+#define MALTA_PCI0_IO_BASE         MALTA_PCIMEM3_BASE
+#define MALTA_PCI0_ADDR( addr )    (MALTA_PCI0_IO_BASE + (addr))
+
+#define MALTA_RTCADR               0x70 // MALTA_PCI_IO_ADDR8(0x70)
+#define MALTA_RTCDAT               0x71 // MALTA_PCI_IO_ADDR8(0x71)
+
+#define MALTA_SMSC_COM1_ADR        0x3f8
+#define MALTA_SMSC_COM2_ADR        0x2f8
+#define MALTA_UART0ADR             MALTA_PCI0_ADDR(MALTA_SMSC_COM1_ADR)
+#define MALTA_UART1ADR             MALTA_SMSC_COM2_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_COM2_ADR)
+
+#define MALTA_SMSC_1284_ADR        0x378
+#define MALTA_1284ADR              MALTA_SMSC_1284_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_1284_ADR)
+
+#define MALTA_SMSC_FDD_ADR         0x3f0
+#define MALTA_FDDADR               MALTA_SMSC_FDD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_FDD_ADR)
+
+#define MALTA_SMSC_KYBD_ADR        0x60  /* Fixed 0x60, 0x64 */
+#define MALTA_KYBDADR              MALTA_SMSC_KYBD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_KYBD_ADR)
+#define MALTA_SMSC_MOUSE_ADR       MALTA_SMSC_KYBD_ADR
+#define MALTA_MOUSEADR             MALTA_KYBDADR
+
+
+#define	MALTA_DMA_PCI_PCIBASE	0x00000000UL
+#define	MALTA_DMA_PCI_PHYSBASE	0x00000000UL
+#define	MALTA_DMA_PCI_SIZE	(256 * 1024 * 1024)
+
+#define	MALTA_DMA_ISA_PCIBASE	0x00800000UL
+#define	MALTA_DMA_ISA_PHYSBASE	0x00000000UL
+#define	MALTA_DMA_ISA_SIZE	(8 * 1024 * 1024)
+
+#ifndef _LOCORE
+void	led_bar(uint8_t);
+void	led_display_word(uint32_t);
+void	led_display_str(const char *);
+void	led_display_char(int, uint8_t);
+#endif
diff --git a/sys/mips/malta/obio.c b/sys/mips/malta/obio.c
new file mode 100644
index 0000000..9e2fd7e
--- /dev/null
+++ b/sys/mips/malta/obio.c
@@ -0,0 +1,185 @@
+/*	$NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $	*/
+
+/*-
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * On-board device autoconfiguration support for Intel IQ80321
+ * evaluation boards.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+
+#include <mips/mips32/malta/maltareg.h>
+#include <mips/mips32/malta/obiovar.h>
+
+int	obio_probe(device_t);
+int	obio_attach(device_t);
+
+/*
+ * A bit tricky and hackish. Since we need OBIO to rely
+ * on PCI we make it pseudo-pci device. But there should 
+ * be only one such device, so we use this static flag 
+ * to prevent false positives on every realPCI device probe. 
+ */
+static int have_one = 0;
+
+int
+obio_probe(device_t dev)
+{
+	if(!have_one)
+	{
+		have_one = 1;
+		return 0;
+	}
+	else
+		return (ENXIO);
+}
+
+int
+obio_attach(device_t dev)
+{
+	struct obio_softc *sc = device_get_softc(dev);
+
+	sc->oba_st = MIPS_BUS_SPACE_IO;
+	sc->oba_addr = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
+	sc->oba_size = MALTA_PCIMEM3_SIZE;
+	sc->oba_rman.rm_type = RMAN_ARRAY;
+	sc->oba_rman.rm_descr = "OBIO I/O";
+	if (rman_init(&sc->oba_rman) != 0 ||
+	    rman_manage_region(&sc->oba_rman,
+	    sc->oba_addr, sc->oba_addr + sc->oba_size) != 0)
+		panic("obio_attach: failed to set up I/O rman");
+	sc->oba_irq_rman.rm_type = RMAN_ARRAY;
+	sc->oba_irq_rman.rm_descr = "OBIO IRQ";
+
+	/* 
+	 * This module is intended for UART purposes only and
+	 * it's IRQ is 4
+	 */
+	if (rman_init(&sc->oba_irq_rman) != 0 ||
+	    rman_manage_region(&sc->oba_irq_rman, 4, 4) != 0)
+		panic("obio_attach: failed to set up IRQ rman");
+
+	device_add_child(dev, "uart", 0);
+	bus_generic_probe(dev);
+	bus_generic_attach(dev);
+
+	return (0);
+}
+
+static struct resource *
+obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
+    u_long start, u_long end, u_long count, u_int flags)
+{
+	struct resource *rv;
+	struct rman *rm;
+	bus_space_tag_t bt = 0;
+	bus_space_handle_t bh = 0;
+	struct obio_softc *sc = device_get_softc(bus);
+
+	switch (type) {
+	case SYS_RES_IRQ:
+		rm = &sc->oba_irq_rman;
+		break;
+	case SYS_RES_MEMORY:
+		return (NULL);
+	case SYS_RES_IOPORT:
+		rm = &sc->oba_rman;
+		bt = sc->oba_st;
+		bh = sc->oba_addr;
+		start = bh;
+		break;
+	default:
+		return (NULL);
+	}
+
+
+	rv = rman_reserve_resource(rm, start, end, count, flags, child);
+	if (rv == NULL) 
+		return (NULL);
+	if (type == SYS_RES_IRQ)
+		return (rv);
+	rman_set_rid(rv, *rid);
+	rman_set_bustag(rv, bt);
+	rman_set_bushandle(rv, bh);
+	
+	if (0) {
+		if (bus_activate_resource(child, type, *rid, rv)) {
+			rman_release_resource(rv);
+			return (NULL);
+		}
+	}
+	return (rv);
+
+}
+
+static int
+obio_activate_resource(device_t bus, device_t child, int type, int rid,
+    struct resource *r)
+{
+	return (0);
+}
+static device_method_t obio_methods[] = {
+	DEVMETHOD(device_probe, obio_probe),
+	DEVMETHOD(device_attach, obio_attach),
+
+	DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
+	DEVMETHOD(bus_activate_resource, obio_activate_resource),
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
+	{0, 0},
+};
+
+static driver_t obio_driver = {
+	"obio",
+	obio_methods,
+	sizeof(struct obio_softc),
+};
+static devclass_t obio_devclass;
+
+DRIVER_MODULE(obio, pci, obio_driver, obio_devclass, 0, 0);
diff --git a/sys/mips/malta/obiovar.h b/sys/mips/malta/obiovar.h
new file mode 100644
index 0000000..801d461
--- /dev/null
+++ b/sys/mips/malta/obiovar.h
@@ -0,0 +1,58 @@
+/*	$NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $	*/
+
+/*-
+ * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#ifndef _MALTA_OBIOVAR_H_
+#define	_MALTA_OBIOVAR_H_
+
+#include <sys/rman.h>
+
+struct obio_softc {
+	bus_space_tag_t oba_st;		/* bus space tag */
+	bus_addr_t oba_addr;		/* address of device */
+	bus_size_t oba_size;		/* size of device */
+	int oba_width;			/* bus width */
+	int oba_irq;			/* XINT interrupt bit # */
+	struct rman oba_rman;
+	struct rman oba_irq_rman;
+	
+};
+extern struct bus_space obio_bs_tag;
+
+#endif /* _MALTA_OBIOVAR_H_ */
diff --git a/sys/mips/malta/std.malta b/sys/mips/malta/std.malta
new file mode 100644
index 0000000..d7ab116
--- /dev/null
+++ b/sys/mips/malta/std.malta
@@ -0,0 +1,9 @@
+# $FreeBSD$
+files	"../mips32/malta/files.malta"
+
+cpu		CPU_MIPS4KC
+options 	ISA_MIPS32
+options		SOFTFLOAT
+device		pci
+device		ata
+device		atadisk
diff --git a/sys/mips/malta/uart_bus_maltausart.c b/sys/mips/malta/uart_bus_maltausart.c
new file mode 100644
index 0000000..0d95694
--- /dev/null
+++ b/sys/mips/malta/uart_bus_maltausart.c
@@ -0,0 +1,98 @@
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/pci/pcivar.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
+#include <dev/uart/uart_cpu.h>
+
+/*
+ * XXXMIPS:
+ */
+#include <mips/mips32/malta/maltareg.h>
+
+#include "uart_if.h"
+
+static int uart_malta_probe(device_t dev);
+
+extern struct uart_class malta_uart_class;
+
+static device_method_t uart_malta_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		uart_malta_probe),
+	DEVMETHOD(device_attach,	uart_bus_attach),
+	DEVMETHOD(device_detach,	uart_bus_detach),
+	{ 0, 0 }
+};
+
+static driver_t uart_malta_driver = {
+	uart_driver_name,
+	uart_malta_methods,
+	sizeof(struct uart_softc),
+};
+
+extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
+static int
+uart_malta_probe(device_t dev)
+{
+	struct uart_softc *sc;
+
+	sc = device_get_softc(dev);
+	sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
+	sc->sc_class = &uart_ns8250_class;
+	bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
+	sc->sc_sysdev->bas.bst = 0;
+	sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
+	sc->sc_bas.bst = 0;
+	sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
+	return(uart_bus_probe(dev, 0, 0, 0, 0));
+}
+
+DRIVER_MODULE(uart, obio, uart_malta_driver, uart_devclass, 0, 0);
diff --git a/sys/mips/malta/uart_cpu_maltausart.c b/sys/mips/malta/uart_cpu_maltausart.c
new file mode 100644
index 0000000..ee5b163
--- /dev/null
+++ b/sys/mips/malta/uart_cpu_maltausart.c
@@ -0,0 +1,82 @@
+/*-
+ * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+/*
+ * Skeleton of this file was based on respective code for ARM
+ * code written by Olivier Houchard.
+ */
+/*
+ * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
+ * experimental and was written for MIPS32 port.
+ */
+#include "opt_uart.h"
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+
+#include <machine/bus.h>
+
+#include <dev/uart/uart.h>
+#include <dev/uart/uart_cpu.h>
+
+#include <mips/mips32/malta/maltareg.h>
+
+bus_space_tag_t uart_bus_space_io;
+bus_space_tag_t uart_bus_space_mem;
+
+extern struct uart_ops malta_usart_ops;
+extern struct bus_space malta_bs_tag;
+
+int
+uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
+{
+	return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
+}
+
+int
+uart_cpu_getdev(int devtype, struct uart_devinfo *di)
+{
+	di->ops = uart_getops(&uart_ns8250_class);
+	di->bas.chan = 0;
+	di->bas.bst = 0;
+	di->bas.regshft = 0;
+	di->bas.rclk = 0;
+	di->baudrate = 115200;
+	di->databits = 8;
+	di->stopbits = 1;
+	di->parity = UART_PARITY_NONE;
+
+	uart_bus_space_io = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
+	uart_bus_space_mem = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
+	di->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
+	return (0);
+}
diff --git a/sys/mips/malta/yamon.c b/sys/mips/malta/yamon.c
new file mode 100644
index 0000000..71ea109
--- /dev/null
+++ b/sys/mips/malta/yamon.c
@@ -0,0 +1,65 @@
+/*-
+ * Copyright (c) 2006 Fill this file and put your name here
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification, immediately at the beginning of the file.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <mips/mips32/malta/yamon.h>
+
+char *
+yamon_getenv(char *name)
+{
+	char *value;
+	yamon_env_t *p;
+
+	value = NULL;
+	for (p = *fenvp; p->name != NULL; ++p) {
+	    if (!strcmp(name, p->name)) {
+		value = p->value;
+		break;
+	    }
+	}
+
+	return (value);
+}
+
+uint32_t
+yamon_getcpufreq(void)
+{
+	uint32_t freq;
+	int ret;
+
+	ret = YAMON_SYSCON_READ(SYSCON_BOARD_CPU_CLOCK_FREQ_ID, &freq,
+	    sizeof(freq));
+	if (ret != 0)
+		freq = 0;
+
+	return (freq);
+}
diff --git a/sys/mips/malta/yamon.h b/sys/mips/malta/yamon.h
new file mode 100644
index 0000000..6970510
--- /dev/null
+++ b/sys/mips/malta/yamon.h
@@ -0,0 +1,93 @@
+/*-
+ * Copyright 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _MALTA_YAMON_H_
+#define _MALTA_YAMON_H_
+
+#define YAMON_FUNCTION_BASE	0x1fc00500
+
+#define YAMON_PRINT_COUNT_OFS	(YAMON_FUNCTION_BASE + 0x04)
+#define YAMON_EXIT_OFS		(YAMON_FUNCTION_BASE + 0x20)
+#define YAMON_FLUSH_CACHE_OFS	(YAMON_FUNCTION_BASE + 0x2c)
+#define YAMON_PRINT_OFS		(YAMON_FUNCTION_BASE + 0x34)
+#define YAMON_REG_CPU_ISR_OFS	(YAMON_FUNCTION_BASE + 0x38)
+#define YAMON_DEREG_CPU_ISR_OFS	(YAMON_FUNCTION_BASE + 0x3c)
+#define YAMON_REG_IC_ISR_OFS	(YAMON_FUNCTION_BASE + 0x40)
+#define YAMON_DEREG_IC_ISR_OFS	(YAMON_FUNCTION_BASE + 0x44)
+#define YAMON_REG_ESR_OFS	(YAMON_FUNCTION_BASE + 0x48)
+#define YAMON_DEREG_ESR_OFS	(YAMON_FUNCTION_BASE + 0x4c)
+#define YAMON_GETCHAR_OFS	(YAMON_FUNCTION_BASE + 0x50)
+#define YAMON_SYSCON_READ_OFS	(YAMON_FUNCTION_BASE + 0x54)
+
+#define YAMON_FUNC(ofs)		(*(uint32_t *)(MIPS_PHYS_TO_KSEG0(ofs)))
+
+typedef void (*t_yamon_print_count)(uint32_t port, char *s, uint32_t count);
+#define YAMON_PRINT_COUNT(s, count) \
+	((t_yamon_print_count)(YAMON_FUNC(YAMON_PRINT_COUNT_OFS)))(0, s, count)
+
+typedef void (*t_yamon_exit)(uint32_t rc);
+#define YAMON_EXIT(rc) ((t_yamon_exit)(YAMON_FUNC(YAMON_EXIT_OFS)))(rc)
+
+typedef void (*t_yamon_print)(uint32_t port, const char *s);
+#define YAMON_PRINT(s) ((t_yamon_print)(YAMON_FUNC(YAMON_PRINT_OFS)))(0, s)
+
+typedef int (*t_yamon_getchar)(uint32_t port, char *ch);
+#define YAMON_GETCHAR(ch) \
+	((t_yamon_getchar)(YAMON_FUNC(YAMON_GETCHAR_OFS)))(0, ch)
+
+typedef int t_yamon_syscon_id;
+typedef int (*t_yamon_syscon_read)(t_yamon_syscon_id id, void *param,
+				   uint32_t size);
+#define YAMON_SYSCON_READ(id, param, size)				\
+	((t_yamon_syscon_read)(YAMON_FUNC(YAMON_SYSCON_READ_OFS)))	\
+	(id, param, size)
+
+typedef struct {
+	char *name;
+	char *value;
+} yamon_env_t;
+
+#define SYSCON_BOARD_CPU_CLOCK_FREQ_ID	34	/* UINT32 */
+#define SYSCON_BOARD_BUS_CLOCK_FREQ_ID	35	/* UINT32 */
+#define SYSCON_BOARD_PCI_FREQ_KHZ_ID	36	/* UINT32 */
+
+char*		yamon_getenv(char *name);
+uint32_t	yamon_getcpufreq(void);
+
+extern yamon_env_t *fenvp[];
+
+#endif /* _MALTA_YAMON_H_ */