diff options
| author | adrian <adrian@FreeBSD.org> | 2011-07-16 00:30:23 +0000 |
|---|---|---|
| committer | adrian <adrian@FreeBSD.org> | 2011-07-16 00:30:23 +0000 |
| commit | 2d5817167b1945bae3a10d42fa3287571a882c3d (patch) | |
| tree | 3f5347932d5b5a4108ff70abf9d5f9fcb8db4742 /sys/mips/malta | |
| parent | 54059df322bae32a98d46cca7127674de6283d41 (diff) | |
| download | FreeBSD-src-2d5817167b1945bae3a10d42fa3287571a882c3d.zip FreeBSD-src-2d5817167b1945bae3a10d42fa3287571a882c3d.tar.gz | |
The i8259 controller is initialized incorrectly on MALTA. It writes
mask bits to control register and control bits to mask register.
The former causes ICW1_RESET|ICW1_LTIM combination to be written to
control register, which on QEMU results in "level sensitive irq not
supported" error.
Submitted by: Robert Millan <rmh@debian.org>
Diffstat (limited to 'sys/mips/malta')
| -rw-r--r-- | sys/mips/malta/gt_pci.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/sys/mips/malta/gt_pci.c b/sys/mips/malta/gt_pci.c index 237e742..aa28639 100644 --- a/sys/mips/malta/gt_pci.c +++ b/sys/mips/malta/gt_pci.c @@ -326,15 +326,15 @@ gt_pci_attach(device_t dev) ICW4_8086); /* mask all interrupts */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, sc->sc_imask & 0xff); /* enable special mask mode */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, OCW3_SEL | OCW3_ESMM | OCW3_SMM); /* read IRR by default */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, OCW3_SEL | OCW3_RR); /* reset, program device, 4 bytes */ @@ -348,15 +348,15 @@ gt_pci_attach(device_t dev) ICW4_8086); /* mask all interrupts */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, sc->sc_imask & 0xff); /* enable special mask mode */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, OCW3_SEL | OCW3_ESMM | OCW3_SMM); /* read IRR by default */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, OCW3_SEL | OCW3_RR); /* |
