Merge from projects/mips to head by hand:

r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines
Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP.  Provide a missing prototype.

r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines
With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
 making it run ;-)

r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines
Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
   intr_machdep.c.  This allows us to have an architecture dependant
   intr_machdep.c (which we will need for RMI) in the machine specific
   directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
   may need to look at finding a better place to put this. But first I want to
   get this thing compiling.

r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines
- Clean out some XXXMIPS comments that's not relevant now

r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines
Fix style error replicated multiple times.  Move to
mips_bus_space_generic for octeon obio impl.

r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines
Don't force ISA_MIPS32.

r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines
Make the yamon function pointer stuff 64-bit safe.  Make the base
unsigned long, and sign extend the address of the function we're
calling through.

r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines
Addresses should be unsigned long.  Make the address constants
unsigned long.

r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines
- Do not use hardcoded uart speed
- Call mips_timer_early_init before initializing uart in order
    to make DELAY usable for ns8250 driver
Submitted by:	Neelkanth Natu

r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines
- Fix prototypes to make compiler happy

r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines
- Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default
   we assume that there is no FPU, because majority of SoC does
   not have it.

r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines
- Provide proper pre_thread/post_ithread functions for GT PCI
    controller.

r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines
- Make mips_bus_space_generic be of type bus_space_tag_t instead of
    struct bus_space and update all relevant places.

r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines
Use FreeBSD/arm approach for handling bus space access: space tag is a pointer
to bus_space structure that defines access methods and hence every bus can
define own accessors. Default space is mips_bus_space_generic. It's a simple
interface to physical memory, values are read with regard to host system
byte order.

1 files changed, 12 insertions, 12 deletions

diff --git a/sys/mips/malta/maltareg.h b/sys/mips/malta/maltareg.h
index f2a7d08..c311d30 100644
--- a/sys/mips/malta/maltareg.h
+++ b/sys/mips/malta/maltareg.h
@@ -94,37 +94,37 @@
 		15	Secondary IDE	Secondary IDE slot/Compact flash connector
  */
 
-#define	MALTA_SYSTEMRAM_BASE	0x00000000  /* System RAM:	*/
+#define	MALTA_SYSTEMRAM_BASE	0x00000000ul  /* System RAM:	*/
 #define	MALTA_SYSTEMRAM_SIZE	0x08000000  /*   128 MByte	*/
 
-#define	MALTA_PCIMEM1_BASE	0x08000000  /* PCI 1 memory:	*/
+#define	MALTA_PCIMEM1_BASE	0x08000000ul  /* PCI 1 memory:	*/
 #define	MALTA_PCIMEM1_SIZE	0x08000000  /*   128 MByte	*/
 
-#define	MALTA_PCIMEM2_BASE	0x10000000  /* PCI 2 memory:	*/
+#define	MALTA_PCIMEM2_BASE	0x10000000ul  /* PCI 2 memory:	*/
 #define	MALTA_PCIMEM2_SIZE	0x08000000  /*   128 MByte	*/
 
-#define	MALTA_PCIMEM3_BASE	0x18000000  /* PCI 3 memory	*/
+#define	MALTA_PCIMEM3_BASE	0x18000000ul  /* PCI 3 memory	*/
 #define	MALTA_PCIMEM3_SIZE	0x03e00000  /*    62 MByte	*/
 
-#define	MALTA_CORECTRL_BASE	0x1be00000  /* Core control:	*/
+#define	MALTA_CORECTRL_BASE	0x1be00000ul  /* Core control:	*/
 #define	MALTA_CORECTRL_SIZE	0x00200000  /*     2 MByte	*/
 
-#define	MALTA_RESERVED_BASE1	0x1c000000  /* Reserved:	*/
+#define	MALTA_RESERVED_BASE1	0x1c000000ul  /* Reserved:	*/
 #define	MALTA_RESERVED_SIZE1	0x02000000  /*    32 MByte	*/
 
-#define	MALTA_MONITORFLASH_BASE	0x1e000000  /* Monitor Flash:	*/
+#define	MALTA_MONITORFLASH_BASE	0x1e000000ul  /* Monitor Flash:	*/
 #define	MALTA_MONITORFLASH_SIZE	0x003e0000  /*     4 MByte	*/
 #define	MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
 
-#define	MALTA_FILEFLASH_BASE	0x1e3e0000 /* File Flash (for monitor): */
+#define	MALTA_FILEFLASH_BASE	0x1e3e0000ul /* File Flash (for monitor): */
 #define	MALTA_FILEFLASH_SIZE	0x00020000 /*   128 KByte	*/
 
 #define	MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB	*/
 
-#define	MALTA_RESERVED_BASE2	0x1e400000  /* Reserved:	*/
+#define	MALTA_RESERVED_BASE2	0x1e400000ul  /* Reserved:	*/
 #define	MALTA_RESERVED_SIZE2	0x00c00000  /*    12 MByte	*/
 
-#define	MALTA_FPGA_BASE		0x1f000000  /* FPGA:		*/
+#define	MALTA_FPGA_BASE		0x1f000000ul  /* FPGA:		*/
 #define	MALTA_FPGA_SIZE		0x00c00000  /*    12 MByte	*/
 
 #define	MALTA_NMISTATUS		(MALTA_FPGA_BASE + 0x24)
@@ -191,10 +191,10 @@
 #define	MALTA_I2COUT		0x10
 #define	MALTA_I2CSEL		0x18
 
-#define	MALTA_BOOTROM_BASE	0x1fc00000  /* Boot ROM:	*/
+#define	MALTA_BOOTROM_BASE	0x1fc00000ul  /* Boot ROM:	*/
 #define	MALTA_BOOTROM_SIZE	0x00400000  /*     4 MByte	*/
 
-#define	MALTA_REVISION		0x1fc00010
+#define	MALTA_REVISION		0x1fc00010ul
 #define	 MALTA_REV_FPGRV	 0xff0000	/* CBUS FPGA revision */
 #define	 MALTA_REV_CORID	 0x00fc00	/* Core Board ID */
 #define	 MALTA_REV_CORRV	 0x000300	/* Core Board Revision */