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| author | gnn <gnn@FreeBSD.org> | 2010-03-03 15:05:58 +0000 |
|---|---|---|
| committer | gnn <gnn@FreeBSD.org> | 2010-03-03 15:05:58 +0000 |
| commit | acf511e4d0cb788a9a050ea1aefef0548aa329ab (patch) | |
| tree | 42725ebf07ce966c74facdca56635db531cdc299 /sys/mips/include/cpufunc.h | |
| parent | 8fcfbfddca984ab42754b8807ddd5edfd7de8fbf (diff) | |
| download | FreeBSD-src-acf511e4d0cb788a9a050ea1aefef0548aa329ab.zip FreeBSD-src-acf511e4d0cb788a9a050ea1aefef0548aa329ab.tar.gz | |
Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.
Add macros for properly accessing coprocessor 0 registers that
support performance counters.
Reviewed by: jkoshy rpaulo fabien imp
MFC after: 1 month
Diffstat (limited to 'sys/mips/include/cpufunc.h')
| -rw-r--r-- | sys/mips/include/cpufunc.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sys/mips/include/cpufunc.h b/sys/mips/include/cpufunc.h index cd4d3e5..d4ca0f1 100644 --- a/sys/mips/include/cpufunc.h +++ b/sys/mips/include/cpufunc.h @@ -244,6 +244,13 @@ MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 1); MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 2); MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 3); + +MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 0); +MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 1); +MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 2); +MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 3); + + #undef MIPS_RDRW32_COP0 static __inline register_t |
