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authorjchandra <jchandra@FreeBSD.org>2011-01-13 15:17:29 +0000
committerjchandra <jchandra@FreeBSD.org>2011-01-13 15:17:29 +0000
commit564c9a855eee850b6f252549bbb5ec6af6ba778a (patch)
tree088c80e0e190da6dd7f15ceb0535eecfaf39addf /sys/mips/include/cache_mipsNN.h
parent267bbb010596a8758a3d64f44dc570be2e5ed5aa (diff)
downloadFreeBSD-src-564c9a855eee850b6f252549bbb5ec6af6ba778a.zip
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Support for 64 bit PTEs on n32 and n64 compilation.
In n32 and n64, add support for physical address above 4GB by having 64 bit page table entries and physical addresses. Major changes are: - param.h: update PTE sizes, masks and shift values to support 64 bit PTEs. - param.h: remove DELAY(), mips_btop(same as atop), mips_ptob (same as ptoa), and reformat. - param.h: remove casting to unsigned long in trunc_page and round_page since this will be used on physical addresses. - _types.h: have 64 bit __vm_paddr_t for n32. - pte.h: update TLB LO0/1 access macros to support 64 bit PTE - pte.h: assembly macros for PTE operations. - proc.h: md_upte is now 64 bit for n32 and n64. - exception.S and swtch.S: use the new PTE macros for PTE operations. - cpufunc.h: TLB_LO0/1 registers are 64bit for n32 and n64. - xlr_machdep.c: Add memory segments above 4GB to phys_avail[] as they are supported now. Reviewed by: jmallett (earlier version)
Diffstat (limited to 'sys/mips/include/cache_mipsNN.h')
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