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| author | adrian <adrian@FreeBSD.org> | 2015-03-21 06:00:46 +0000 |
|---|---|---|
| committer | adrian <adrian@FreeBSD.org> | 2015-03-21 06:00:46 +0000 |
| commit | f5a9460e2b53dc286f9dc96e32ce68b5e60b7f09 (patch) | |
| tree | fb1cf2e64f0d29e51a13fc336e2dbf9195840c64 /sys/mips/atheros | |
| parent | 9ce94e7c252c7fd3c1072e735823abac4782fe02 (diff) | |
| download | FreeBSD-src-f5a9460e2b53dc286f9dc96e32ce68b5e60b7f09.zip FreeBSD-src-f5a9460e2b53dc286f9dc96e32ce68b5e60b7f09.tar.gz | |
add QCA955x PCIe configuration registers.
These are /not/ absolute addresses, as the QCA955x SoC has 2 PCIe RC's
(and 1 PCIe EP.)
Diffstat (limited to 'sys/mips/atheros')
| -rw-r--r-- | sys/mips/atheros/qca955xreg.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/sys/mips/atheros/qca955xreg.h b/sys/mips/atheros/qca955xreg.h index 555070d..c1056b4 100644 --- a/sys/mips/atheros/qca955xreg.h +++ b/sys/mips/atheros/qca955xreg.h @@ -205,4 +205,14 @@ #define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8) #define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac) +/* PCIe control block - relative to PCI_CTRL_BASE0/PCI_CTRL_BASE1 */ + +#define QCA955X_PCI_APP 0x0 +#define QCA955X_PCI_APP_LTSSM_ENABLE (1 << 0) +#define QCA955X_PCI_RESET 0x18 +#define QCA955X_PCI_RESET_LINK_UP (1 << 0) +#define QCA955X_PCI_INTR_STATUS 0x4c +#define QCA955X_PCI_INTR_MASK 0x50 +#define QCA955X_PCI_INTR_DEV0 (1 << 14) + #endif /* __QCA955XREG_H__ */ |
