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| author | adrian <adrian@FreeBSD.org> | 2015-07-03 03:32:54 +0000 |
|---|---|---|
| committer | adrian <adrian@FreeBSD.org> | 2015-07-03 03:32:54 +0000 |
| commit | d584d71770f0c814ff9ea216fa4e3f059c288de1 (patch) | |
| tree | fa358e0ef50c617c6cff6383a58dad7b3b2b6977 /sys/mips/atheros | |
| parent | c9fadd2c5d34edf3328f98c47a1a6d3f6208f581 (diff) | |
| download | FreeBSD-src-d584d71770f0c814ff9ea216fa4e3f059c288de1.zip FreeBSD-src-d584d71770f0c814ff9ea216fa4e3f059c288de1.tar.gz | |
Add register defines for the QCA955x DDR flush and GPIO control.
Diffstat (limited to 'sys/mips/atheros')
| -rw-r--r-- | sys/mips/atheros/qca955xreg.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/sys/mips/atheros/qca955xreg.h b/sys/mips/atheros/qca955xreg.h index c1056b4..a082708 100644 --- a/sys/mips/atheros/qca955xreg.h +++ b/sys/mips/atheros/qca955xreg.h @@ -179,6 +179,13 @@ #define QCA955X_RESET_I2S BIT(0) /* GPIO block */ +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA955X_GPIO_REG_FUNC 0x6c #define QCA955X_GPIO_COUNT 24 #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) @@ -204,6 +211,10 @@ #define QCA955X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4) #define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8) #define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac) +/* PCIe EP */ +#define QCA955X_DDR_REG_FLUSH_SRC1 (AR71XX_APB_BSAE + 0xb0) +/* checksum engine */ +#define QCA955X_DDR_REG_FLUSH_SRC2 (AR71XX_APB_BSAE + 0xb2) /* PCIe control block - relative to PCI_CTRL_BASE0/PCI_CTRL_BASE1 */ |
