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authoradrian <adrian@FreeBSD.org>2013-07-21 03:51:24 +0000
committeradrian <adrian@FreeBSD.org>2013-07-21 03:51:24 +0000
commit63418609bdd239cffe61924ea2ead81b0e078fba (patch)
treeea272248c474faf5c81d5a3087e8930469a2a0ce /sys/mips/atheros
parent51bcea9c2c72d61c7bbc8c48156326accb7d4a95 (diff)
downloadFreeBSD-src-63418609bdd239cffe61924ea2ead81b0e078fba.zip
FreeBSD-src-63418609bdd239cffe61924ea2ead81b0e078fba.tar.gz
Add two new CPU specific definitions - the watchdog clock frequency and
the UART clock frequency. The AR933x and AR934x have separate PLL settings for these.
Diffstat (limited to 'sys/mips/atheros')
-rw-r--r--sys/mips/atheros/ar71xx_cpudef.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/sys/mips/atheros/ar71xx_cpudef.h b/sys/mips/atheros/ar71xx_cpudef.h
index bd88022..a30157c 100644
--- a/sys/mips/atheros/ar71xx_cpudef.h
+++ b/sys/mips/atheros/ar71xx_cpudef.h
@@ -121,10 +121,14 @@ extern uint32_t u_ar71xx_refclk;
extern uint32_t u_ar71xx_cpu_freq;
extern uint32_t u_ar71xx_ahb_freq;
extern uint32_t u_ar71xx_ddr_freq;
+extern uint32_t u_ar71xx_uart_freq;
+extern uint32_t u_ar71xx_wdt_freq;
static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; }
static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; }
static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; }
static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; }
-
+static inline uint64_t ar71xx_uart_freq(void) { return u_ar71xx_uart_freq; }
+static inline uint64_t ar71xx_wdt_freq(void) { return u_ar71xx_wdt_freq; }
+
#endif
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