diff options
| author | gonzo <gonzo@FreeBSD.org> | 2009-11-06 06:50:45 +0000 |
|---|---|---|
| committer | gonzo <gonzo@FreeBSD.org> | 2009-11-06 06:50:45 +0000 |
| commit | 5435db6c0619c871e76087e53fd43163fb528237 (patch) | |
| tree | 61c80a9b1b93fbf4aec9ab7cc614e19a2acb1b76 /sys/mips/atheros/if_arge.c | |
| parent | 7fe49d2c3fd033a291826d6b4699c33142d88506 (diff) | |
| download | FreeBSD-src-5435db6c0619c871e76087e53fd43163fb528237.zip FreeBSD-src-5435db6c0619c871e76087e53fd43163fb528237.tar.gz | |
- Fix initialization of PLL registers (different shifts for
arge0/arge1)
- Use base MAC address to generate MACs for arge1 and above
Diffstat (limited to 'sys/mips/atheros/if_arge.c')
| -rw-r--r-- | sys/mips/atheros/if_arge.c | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/sys/mips/atheros/if_arge.c b/sys/mips/atheros/if_arge.c index b16a088..95e0c12 100644 --- a/sys/mips/atheros/if_arge.c +++ b/sys/mips/atheros/if_arge.c @@ -205,9 +205,11 @@ arge_attach(device_t dev) if (sc->arge_mac_unit == 0) { sc->arge_ddr_flush_reg = AR71XX_WB_FLUSH_GE0; sc->arge_pll_reg = AR71XX_PLL_ETH_INT0_CLK; + sc->arge_pll_reg_shift = 17; } else { sc->arge_ddr_flush_reg = AR71XX_WB_FLUSH_GE1; sc->arge_pll_reg = AR71XX_PLL_ETH_INT1_CLK; + sc->arge_pll_reg_shift = 19; } /* @@ -229,7 +231,6 @@ arge_attach(device_t dev) sc->arge_phy_num = phynum; - mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0); @@ -308,6 +309,9 @@ arge_attach(device_t dev) eaddr[5] = (rnd >> 8) & 0xff; } + if (sc->arge_mac_unit != 0) + eaddr[5] += sc->arge_mac_unit; + if (arge_dma_alloc(sc) != 0) { error = ENXIO; goto fail; @@ -617,20 +621,20 @@ arge_link_task(void *arg, int pending) /* set PLL registers */ sec_cfg = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG); - sec_cfg &= ~(3 << 17); - sec_cfg |= (2 << 17); + sec_cfg &= ~(3 << sc->arge_pll_reg_shift); + sec_cfg |= (2 << sc->arge_pll_reg_shift); - ATH_WRITE_REG(AR71XX_PLL_CPU_CONFIG, sec_cfg); + ATH_WRITE_REG(AR71XX_PLL_SEC_CONFIG, sec_cfg); DELAY(100); ATH_WRITE_REG(sc->arge_pll_reg, pll); - sec_cfg |= (3 << 17); - ATH_WRITE_REG(AR71XX_PLL_CPU_CONFIG, sec_cfg); + sec_cfg |= (3 << sc->arge_pll_reg_shift); + ATH_WRITE_REG(AR71XX_PLL_SEC_CONFIG, sec_cfg); DELAY(100); - sec_cfg &= ~(3 << 17); - ATH_WRITE_REG(AR71XX_PLL_CPU_CONFIG, sec_cfg); + sec_cfg &= ~(3 << sc->arge_pll_reg_shift); + ATH_WRITE_REG(AR71XX_PLL_SEC_CONFIG, sec_cfg); DELAY(100); } } else |
