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authoradrian <adrian@FreeBSD.org>2010-08-19 02:03:12 +0000
committeradrian <adrian@FreeBSD.org>2010-08-19 02:03:12 +0000
commit1c6fde75b32cd476ed4247f4e2870435fb6fe143 (patch)
treeaf5f12c83bfc167d9e173e3a136bae5cae9c3f2b /sys/mips/atheros/ar71xx_setup.c
parent9a8b3cac780596343c946cecea69c661e3615e12 (diff)
downloadFreeBSD-src-1c6fde75b32cd476ed4247f4e2870435fb6fe143.zip
FreeBSD-src-1c6fde75b32cd476ed4247f4e2870435fb6fe143.tar.gz
Preparation work for supporting the AR91xx and AR724x.
* Implement a SoC probe function, from Linux, which determines the SoC family, type and revision. This only probes the AR71xx series SoC and (currently) panics on others. * Migrate some of the AR71XX specific hardware init (USB device, determining system frequencies) into using the cpuops introduced in an earlier commit. Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring, Ethernet PLL setup, other things I've likely missed) will be introduced in subsequent commits. Reviewed by: imp@ Obtained from: (partially) Linux
Diffstat (limited to 'sys/mips/atheros/ar71xx_setup.c')
-rw-r--r--sys/mips/atheros/ar71xx_setup.c119
1 files changed, 119 insertions, 0 deletions
diff --git a/sys/mips/atheros/ar71xx_setup.c b/sys/mips/atheros/ar71xx_setup.c
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+++ b/sys/mips/atheros/ar71xx_setup.c
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+/*-
+ * Copyright (c) 2010 Adrian Chadd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <machine/cpuregs.h>
+
+#include <mips/sentry5/s5reg.h>
+
+#include "opt_ddb.h"
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cons.h>
+#include <sys/kdb.h>
+#include <sys/reboot.h>
+
+#include <vm/vm.h>
+#include <vm/vm_page.h>
+
+#include <net/ethernet.h>
+
+#include <machine/clock.h>
+#include <machine/cpu.h>
+#include <machine/hwfunc.h>
+#include <machine/md_var.h>
+#include <machine/trap.h>
+#include <machine/vmparam.h>
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_setup.h>
+
+#include <mips/atheros/ar71xx_cpudef.h>
+
+#include <mips/atheros/ar71xx_chip.h>
+
+#define AR71XX_SYS_TYPE_LEN 128
+
+static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
+enum ar71xx_soc_type ar71xx_soc;
+struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL;
+
+void
+ar71xx_detect_sys_type(void)
+{
+ char *chip = "????";
+ uint32_t id;
+ uint32_t major;
+ uint32_t minor;
+ uint32_t rev = 0;
+
+ id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);
+ major = id & REV_ID_MAJOR_MASK;
+
+ switch (major) {
+ case REV_ID_MAJOR_AR71XX:
+ minor = id & AR71XX_REV_ID_MINOR_MASK;
+ rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+ rev &= AR71XX_REV_ID_REVISION_MASK;
+ ar71xx_cpu_ops = &ar71xx_chip_def;
+ switch (minor) {
+ case AR71XX_REV_ID_MINOR_AR7130:
+ ar71xx_soc = AR71XX_SOC_AR7130;
+ chip = "7130";
+ break;
+
+ case AR71XX_REV_ID_MINOR_AR7141:
+ ar71xx_soc = AR71XX_SOC_AR7141;
+ chip = "7141";
+ break;
+
+ case AR71XX_REV_ID_MINOR_AR7161:
+ ar71xx_soc = AR71XX_SOC_AR7161;
+ chip = "7161";
+ break;
+ }
+ break;
+
+ default:
+ panic("ar71xx: unknown chip id:0x%08x\n", id);
+ }
+
+ sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
+}
+
+const char *
+ar71xx_get_system_type(void)
+{
+ return ar71xx_sys_type;
+}
+
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