- Add pci bus space that translates byte order to little endian,

    may be it will be merged with bus_space_reversed later
- Handle memory resources close to bus in order to control
    bus_space_tag

1 files changed, 198 insertions, 0 deletions

diff --git a/sys/mips/atheros/ar71xx_pci_bus_space.c b/sys/mips/atheros/ar71xx_pci_bus_space.c
new file mode 100644
index 0000000..5540181
--- /dev/null
+++ b/sys/mips/atheros/ar71xx_pci_bus_space.c
@@ -0,0 +1,198 @@
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+
+#include <machine/bus.h>
+#include <mips/atheros/ar71xx_pci_bus_space.h>
+
+static bs_r_1_s_proto(pcimem);
+static bs_r_2_s_proto(pcimem);
+static bs_r_4_s_proto(pcimem);
+static bs_w_1_s_proto(pcimem);
+static bs_w_2_s_proto(pcimem);
+static bs_w_4_s_proto(pcimem);
+
+/*
+ * Bus space that handles offsets in word for 1/2 bytes read/write access.
+ * Byte order of values is handled by device drivers itself. 
+ */
+static struct bus_space bus_space_pcimem = {
+	/* cookie */
+	(void *) 0,
+
+	/* mapping/unmapping */
+	generic_bs_map,
+	generic_bs_unmap,
+	generic_bs_subregion,
+
+	/* allocation/deallocation */
+	NULL,
+	NULL,
+
+	/* barrier */
+	generic_bs_barrier,
+
+	/* read (single) */
+	generic_bs_r_1,
+	generic_bs_r_2,
+	generic_bs_r_4,
+	NULL,
+
+	/* read multiple */
+	generic_bs_rm_1,
+	generic_bs_rm_2,
+	generic_bs_rm_4,
+	NULL,
+
+	/* read region */
+	generic_bs_rr_1,
+	generic_bs_rr_2,
+	generic_bs_rr_4,
+	NULL,
+
+	/* write (single) */
+	generic_bs_w_1,
+	generic_bs_w_2,
+	generic_bs_w_4,
+	NULL,
+
+	/* write multiple */
+	generic_bs_wm_1,
+	generic_bs_wm_2,
+	generic_bs_wm_4,
+	NULL,
+
+	/* write region */
+	NULL,
+	generic_bs_wr_2,
+	generic_bs_wr_4,
+	NULL,
+
+	/* set multiple */
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+
+	/* set region */
+	NULL,
+	generic_bs_sr_2,
+	generic_bs_sr_4,
+	NULL,
+
+	/* copy */
+	NULL,
+	generic_bs_c_2,
+	NULL,
+	NULL,
+
+	/* read (single) stream */
+	pcimem_bs_r_1_s,
+	pcimem_bs_r_2_s,
+	pcimem_bs_r_4_s,
+	NULL,
+
+	/* read multiple stream */
+	generic_bs_rm_1,
+	generic_bs_rm_2,
+	generic_bs_rm_4,
+	NULL,
+
+	/* read region stream */
+	generic_bs_rr_1,
+	generic_bs_rr_2,
+	generic_bs_rr_4,
+	NULL,
+
+	/* write (single) stream */
+	pcimem_bs_w_1_s,
+	pcimem_bs_w_2_s,
+	pcimem_bs_w_4_s,
+	NULL,
+
+	/* write multiple stream */
+	generic_bs_wm_1,
+	generic_bs_wm_2,
+	generic_bs_wm_4,
+	NULL,
+
+	/* write region stream */
+	NULL,
+	generic_bs_wr_2,
+	generic_bs_wr_4,
+	NULL,
+};
+
+bus_space_tag_t ar71xx_bus_space_pcimem = &bus_space_pcimem;
+
+static uint8_t
+pcimem_bs_r_1_s(void *t, bus_space_handle_t h, bus_size_t o)
+{
+
+	return readb(h + (o &~ 3) + (3 - (o & 3)));
+}
+
+static void
+pcimem_bs_w_1_s(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
+{
+
+	writeb(h + (o &~ 3) + (3 - (o & 3)), v);
+}
+
+static uint16_t
+pcimem_bs_r_2_s(void *t, bus_space_handle_t h, bus_size_t o)
+{
+
+	return readw(h + (o &~ 3) + (2 - (o & 3)));
+}
+
+static void
+pcimem_bs_w_2_s(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
+{
+
+	writew(h + (o &~ 3) + (2 - (o & 3)), v);
+}
+
+static uint32_t
+pcimem_bs_r_4_s(void *t, bus_space_handle_t h, bus_size_t o)
+{
+	
+	return le32toh(readl(h + o));
+}
+
+static void
+pcimem_bs_w_4_s(void *t, bus_space_handle_t h, bus_size_t o, uint32_t v)
+{
+
+	writel(h + o, htole32(v));
+}