Properly serialize the global shootdown with the instruction

stream of the local processor. Also explicitly invalidate
the ALAT. This is done on the other CPUs in the coherence
domain by virtue of the ptc.ga instruction, but does not
apply to the local CPU.

2 files changed, 15 insertions, 2 deletions

diff --git a/sys/ia64/ia64/pmap.c b/sys/ia64/ia64/pmap.c
index 411d53a..625d0af7 100644
--- a/sys/ia64/ia64/pmap.c
+++ b/sys/ia64/ia64/pmap.c
@@ -559,10 +559,14 @@ pmap_invalidate_page(vm_offset_t va)
 	} while (sem != tag);
 
 	ia64_ptc_ga(va, PAGE_SHIFT << 2);
+	ia64_mf();
+	ia64_srlz_i();
 
 	/* PTC.G leave exclusive */
 	atomic_store_rel_long(&pmap_ptc_g_sem, 0);
 
+	ia64_invala();
+
 	intr_restore(is);
 	critical_exit();
 }
diff --git a/sys/ia64/include/ia64_cpu.h b/sys/ia64/include/ia64_cpu.h
index bb8284d..74e649b 100644
--- a/sys/ia64/include/ia64_cpu.h
+++ b/sys/ia64/include/ia64_cpu.h
@@ -266,7 +266,7 @@ ia64_ptc_e(uint64_t v)
 static __inline void
 ia64_ptc_g(uint64_t va, uint64_t log2size)
 {
-	__asm __volatile("ptc.g %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
+	__asm __volatile("ptc.g %0,%1;;" :: "r"(va), "r"(log2size));
 }
 
 /*
@@ -275,7 +275,7 @@ ia64_ptc_g(uint64_t va, uint64_t log2size)
 static __inline void
 ia64_ptc_ga(uint64_t va, uint64_t log2size)
 {
-	__asm __volatile("ptc.ga %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
+	__asm __volatile("ptc.ga %0,%1;;" :: "r"(va), "r"(log2size));
 }
 
 /*
@@ -288,6 +288,15 @@ ia64_ptc_l(uint64_t va, uint64_t log2size)
 }
 
 /*
+ * Invalidate the ALAT on the local processor.
+ */
+static __inline void
+ia64_invala(void)
+{
+	__asm __volatile("invala;;");
+}
+
+/*
  * Unordered memory load.
  */